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Clock generator
Known as:
Clock source
, Timing signal generator
A clock generator is a circuit that produces a timing signal (known as a clock signal and behaves as such) for use in synchronizing a circuit's…
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Related topics
Related topics
22 relations
Amplifier
Central processing unit
Clock signal
Crystal oscillator
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2017
Review
2017
Design of a low power ECG signal processor for wearable health system-review and implementation issues
K. Raja
,
S. Saravanan
,
R. Anitha
,
S. Priya
,
R. Subhashini
International Symposium on Combinatorial…
2017
Corpus ID: 16673596
The paper presents a low power ECG signal processing ASIC chip design to extract the ECG features for wearable health system. The…
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2013
2013
R3TOS: A Novel Reliable Reconfigurable Real-Time Operating System for Highly Adaptive, Efficient, and Dependable Computing on FPGAs
X. Iturbe
,
K. Benkrid
,
+5 authors
Jon Perez
IEEE transactions on computers
2013
Corpus ID: 7214034
Despite the clear potential of FPGAs to push the current power wall beyond what is possible with general-purpose processors, as…
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2012
2012
On the low-power design, stability improvement and frequency estimation of the CMOS ring oscillator
Vratislav Michal
Proceedings of 22nd International Conference…
2012
Corpus ID: 11336538
In this paper, a simple method allowing optimization of the CMOS ring oscillator frequency dispersion and power consumption is…
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2010
2010
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs
Xin Zhao
,
S. Lim
Asia and South Pacific Design Automation…
2010
Corpus ID: 901394
In this paper, three effective design techniques are presented to effectively reduce the clock power consumption and slew of the…
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2007
2007
Spread spectrum clock generator
Ping-Ying Wang
,
Shang-Ping Chen
IEEE Asian Solid-State Circuits Conference
2007
Corpus ID: 29660218
In this paper, we present a spread spectrum clock generator which has advantages of 1) Low cost: the loop filter or' the SSCG is…
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Highly Cited
2006
Highly Cited
2006
A 120-MHz–1.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling
Jin-Han Kim
,
Young-Ho Kwak
,
Moo-young Kim
,
Soo-Won Kim
,
Chulwoo Kim
IEEE Journal of Solid-State Circuits
2006
Corpus ID: 40892453
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-mum CMOS technology…
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2003
2003
10GHz clock distribution using coupled standing-wave oscillators
F. O’Mahony
,
C. Yue
,
M. Horowitz
,
S.S. Wong
IEEE International Solid-State Circuits…
2003
Corpus ID: 16560543
A global clock network comprised of coupled, standing-wave oscillators is prototyped in a 0.18/spl mu/m 6M CMOS process. The…
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Highly Cited
2002
Highly Cited
2002
A "flying-adder" architecture of frequency and phase synthesis with scalability
Liming Xiu
,
Zhihong You
IEEE Transactions on Very Large Scale Integration…
2002
Corpus ID: 16846279
Most of today's digital designs, from small-scale digital block designs to system-on-chip (SoC) designs, are based on…
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1995
1995
Defect-oriented test methodology for complex mixed-signal circuits
F. Kuijstermans
,
M. Sachdev
,
A. P. Thijssen
Proceedings the European Design and Test…
1995
Corpus ID: 16169377
Testing of analog blocks in digital circuits is emerging as a critical factor in the success of mixed-signal ICs. The present…
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1993
1993
The Physics of heart and circulation
J. Strackee
,
N. Westerhof
1993
Corpus ID: 18371037
The heart in our body basic aspects of cardiac electrical activity electrocardiography cardiac arrhythmias rhythms and analysis…
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