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Clipper architecture
Known as:
Fairchild Clipper
, Intergraph Clipper
The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much…
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14 relations
CPU cache
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2003
2003
IAC-02-U.5.01 APPLICATION OF THE ABBREVIATED TECHNOLOGY IDENTIFICATION, EVALUATION, AND SELECTION (ATIES) METHODOLOGY TO A MARS ORBIT BASING (MOB) SOLAR CLIPPER ARCHITECTURE
A. Charania
,
J. Olds
,
Clipper Architecture
,
A. C. Charaniaand
,
J. Olds
2003
Corpus ID: 15886528
Strategic decision makers, constrained by limited research budgets, need methods for prioritization of advanced space…
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1994
1994
A CMOS circuit for real-time chip temperature measurement
Steven R. Boyle
,
R. Heald
Proceedings of COMPCON '94
1994
Corpus ID: 20715622
The usual way to measure chip temperature is to measure the forward voltage, V/sub f/, of the temperature-characterized on-chip…
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Review
1988
Review
1988
Book Review: Fairchild Clipper: 32-Bit Microprocessor User's Manual
P. F. Jackson
1988
Corpus ID: 57242869
Fairchild Clipper: 32-bit Microprocessor User's Manual (Prentice-Hall, 1987,457 pp., £19.10) This manual provides comprehensive…
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1987
1987
Introduction to the Clipper Architecture
C. Hunter
IEEE Micro
1987
Corpus ID: 1927728
This 32-bit, three-chip module combines RISC and CISC features with mainframe-style cache and three-phase pipeline designs.
1987
1987
The Fairchild clipper
M. Ackerman
,
G. Baum
1987
Corpus ID: 59675507
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