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Bus network
Known as:
Bus topology
, Linear bus topology
A bus network is a network topology in which nodes are directly connected to a common linear (or branched) half-duplex link called a bus.
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Related topics
Related topics
18 relations
AppleTalk
Bus (computing)
Collision domain
DMX512
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Broader (2)
Network architecture
Network topology
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2020
2020
Improved Coyote Optimization Algorithm for Optimally Installing Solar Photovoltaic Distribution Generation Units in Radial Distribution Power Systems
T. Nguyen
,
Thai Dinh Pham
,
L. Kien
,
L. Dai
Complex
2020
Corpus ID: 212423370
This paper proposes an improved coyote optimization algorithm (ICOA) for optimizing the location and sizing of solar photovoltaic…
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2015
2015
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
Hyun-Jin Kim
,
Jeong-Don Lim
,
+27 authors
Jeong-Hyuk Choi
IEEE International Solid-State Circuits…
2015
Corpus ID: 25336641
NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and…
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2007
2007
Divisible Load Scheduling: An Approach Using Coalitional Games
T. E. Carroll
,
Daniel Grosu
International Symposium on Parallel and…
2007
Corpus ID: 2193089
Scheduling divisible loads in distributed systems is the subject of divisible load theory (DLT). In this paper we show that…
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Review
2006
Review
2006
PAC DSP Core and Application Processors
David Chih-Wei Chang
,
I-Tao Liao
,
Jenq Kuen Lee
,
Wen-Feng Chen
,
S. Tseng
,
C. Jen
IEEE International Conference on Multimedia and…
2006
Corpus ID: 8029106
This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial…
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2005
2005
A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus
Jongsun Kim
,
I. Verbauwhede
,
Mau-Chung Frank Chang
IEEE Journal of Solid-State Circuits
2005
Corpus ID: 93615
This paper describes a low-power synchronous pulsed signaling scheme on a fully AC coupled multidrop bus for board-level chip-to…
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2003
2003
An optical centralized shared-bus architecture demonstrator for microprocessor-to-memory interconnects
Xuliang Han
,
G. Kim
,
G. Lipovski
,
Ray T. Chen
2003
Corpus ID: 15519660
An architecture demonstrator of an innovative interconnect scheme called the optical centralized shared-bus is presented. This…
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2000
2000
Parallel Processor Configuration Design with Processing/Transmission Costs
S. Charcranoon
,
T. Robertazzi
,
S. Luryi
IEEE Trans. Computers
2000
Corpus ID: 13146361
A computer configuration design problem where the objective is to configure a parallel processor to do processing in a cost…
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1996
1996
RMB-a reconfigurable multiple bus network
H. ElGindy
,
Arun Kumar Somani
,
Heiko Schröder
,
H. Schmeck
,
A. Spray
Proceedings. Second International Symposium on…
1996
Corpus ID: 21602703
The heart of a massively parallel computer is its interconnection network. In this article we present a reconfigurable multiple…
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Highly Cited
1994
Highly Cited
1994
Fault-Tolerant Multiprocessor Link and Bus Network Architectures
D. Pradhan
IEEE transactions on computers
1994
Corpus ID: 31556838
This paper presents a general class of regular networks which provide optimal (near-optimal) fault tolerance.
Highly Cited
1991
Highly Cited
1991
Resource allocation in a dynamically partitionable bus network using a graph coloring algorithm
Tai-Kuo Woo
,
S. Su
,
R. Newman
IEEE Transactions on Communications
1991
Corpus ID: 2225754
An efficient dynamic graph traversal algorithm is used to identify nonconflicting requests and to allocate network resources in a…
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