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Bus network
Known as:
Bus topology
, Linear bus topology
A bus network is a network topology in which nodes are directly connected to a common linear (or branched) half-duplex link called a bus.
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Related topics
Related topics
18 relations
AppleTalk
Bus (computing)
Collision domain
DMX512
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Broader (2)
Network architecture
Network topology
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
Hyun-Jin Kim
,
Jeong-Don Lim
,
+27 authors
Jeong-Hyuk Choi
IEEE International Solid-State Circuits…
2015
Corpus ID: 25336641
NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and…
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2015
2015
Patch-based Modelling of City-centre Bus Movement with Phase-type Distributions
Daniël Reijsbergen
,
S. Gilmore
,
J. Hillston
PASM
2015
Corpus ID: 13775145
2010
2010
An Embedded CAN-BUS Communication Module for Measurement and Control System
Xiaoming Li
,
Ming-xia Li
International Conference on E-Learning, E…
2010
Corpus ID: 11021900
A CAN-BUS communication module for embedded system has been proposed in this paper, together with its hardware and software…
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2008
2008
Time Dependent Message Spraying for Routing in Intermittently Connected Networks
E. Bulut
,
Zijian Wang
,
B. Szymański
IEEE GLOBECOM - IEEE Global Telecommunications…
2008
Corpus ID: 1046909
Intermittently connected mobile networks, also called delay tolerant networks (DTNs), are wireless networks in which at any given…
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Review
2006
Review
2006
PAC DSP Core and Application Processors
David Chih-Wei Chang
,
I-Tao Liao
,
Jenq Kuen Lee
,
Wen-Feng Chen
,
S. Tseng
,
C. Jen
IEEE International Conference on Multimedia and…
2006
Corpus ID: 8029106
This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial…
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2000
2000
Parallel Processor Configuration Design with Processing/Transmission Costs
S. Charcranoon
,
T. Robertazzi
,
S. Luryi
IEEE Trans. Computers
2000
Corpus ID: 13146361
A computer configuration design problem where the objective is to configure a parallel processor to do processing in a cost…
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1996
1996
RMB-a reconfigurable multiple bus network
H. ElGindy
,
Arun Kumar Somani
,
Heiko Schröder
,
H. Schmeck
,
A. Spray
Proceedings. Second International Symposium on…
1996
Corpus ID: 21602703
The heart of a massively parallel computer is its interconnection network. In this article we present a reconfigurable multiple…
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1994
1994
Effect of fault tolerance and communication delay on response time in a multiprocessor system with a bus topology
S. Bataineh
,
M. Al-Ibrahim
Computer Communications
1994
Corpus ID: 205035211
Highly Cited
1994
Highly Cited
1994
Fault-Tolerant Multiprocessor Link and Bus Network Architectures
D. Pradhan
IEEE transactions on computers
1994
Corpus ID: 31556838
This paper presents a general class of regular networks which provide optimal (near-optimal) fault tolerance.
1986
1986
CSMA/CD-based protocol with dynamic segmentation
K. Chua
,
K. Lye
,
C. Ko
Computer Communications
1986
Corpus ID: 19982297
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