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Bus network
Known as:
Bus topology
, Linear bus topology
A bus network is a network topology in which nodes are directly connected to a common linear (or branched) half-duplex link called a bus.
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Related topics
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18 relations
AppleTalk
Bus (computing)
Collision domain
DMX512
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Broader (2)
Network architecture
Network topology
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
Hyun-Jin Kim
,
Jeong-Don Lim
,
+27 authors
Jeong-Hyuk Choi
IEEE International Solid-State Circuits…
2015
Corpus ID: 25336641
NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and…
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2011
2011
A New High-Speed Bus Topology LAN Protocol Compatible with CAN
Ryo Kurachi
,
H. Takada
,
Masanobu Nishimura
,
S. Horihata
2011
Corpus ID: 62741615
Review
2006
Review
2006
PAC DSP Core and Application Processors
David Chih-Wei Chang
,
I-Tao Liao
,
Jenq Kuen Lee
,
Wen-Feng Chen
,
S. Tseng
,
C. Jen
IEEE International Conference on Multimedia and…
2006
Corpus ID: 8029106
This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial…
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2006
2006
Efficient exploration of bus-based system-on-chip architectures
Sungchan Kim
,
S. Ha
IEEE Transactions on Very Large Scale Integration…
2006
Corpus ID: 15416273
Separation between computation and communication in system design allows system designers to explore the communication…
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2003
2003
An optical centralized shared-bus architecture demonstrator for microprocessor-to-memory interconnects
Xuliang Han
,
G. Kim
,
G. Lipovski
,
Ray T. Chen
2003
Corpus ID: 15519660
An architecture demonstrator of an innovative interconnect scheme called the optical centralized shared-bus is presented. This…
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2000
2000
Parallel Processor Configuration Design with Processing/Transmission Costs
S. Charcranoon
,
T. Robertazzi
,
S. Luryi
IEEE Trans. Computers
2000
Corpus ID: 13146361
A computer configuration design problem where the objective is to configure a parallel processor to do processing in a cost…
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1996
1996
RMB-a reconfigurable multiple bus network
H. ElGindy
,
Arun Kumar Somani
,
Heiko Schröder
,
H. Schmeck
,
A. Spray
Proceedings. Second International Symposium on…
1996
Corpus ID: 21602703
The heart of a massively parallel computer is its interconnection network. In this article we present a reconfigurable multiple…
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1994
1994
Effect of fault tolerance and communication delay on response time in a multiprocessor system with a bus topology
S. Bataineh
,
M. Al-Ibrahim
Computer Communications
1994
Corpus ID: 205035211
Highly Cited
1994
Highly Cited
1994
Fault-Tolerant Multiprocessor Link and Bus Network Architectures
D. Pradhan
IEEE transactions on computers
1994
Corpus ID: 31556838
This paper presents a general class of regular networks which provide optimal (near-optimal) fault tolerance.
1993
1993
Power distribution synthesis for analog and mixed-signal ASICs in RAIL
B. Stanisic
,
Rob A. Rutenbar
,
L. Carley
Proceedings of IEEE Custom Integrated Circuits…
1993
Corpus ID: 62325408
The authors present new power distribution synthesis techniques that can handle realistic analog and mixed-signal performance…
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