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Bus network

Known as: Bus topology, Linear bus topology 
A bus network is a network topology in which nodes are directly connected to a common linear (or branched) half-duplex link called a bus.
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Related topics

Related topics

18 relations
AppleTalkBus (computing)Collision domainDMX512

Broader (2)

Network architectureNetwork topology

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip
NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and… 
Review
2012
Review
2012
Comparison of efficiency of two dc-to-ac converters for grid connected solar applications
In this paper; requirements from grid connected photovoltaic (PV) converters are briefly reviewed. Traditional buck-converter… 
2011
2011
A New High-Speed Bus Topology LAN Protocol Compatible with CAN
2007
2007
Divisible Load Scheduling: An Approach Using Coalitional Games
Scheduling divisible loads in distributed systems is the subject of divisible load theory (DLT). In this paper we show that… 
Review
2006
Review
2006
PAC DSP Core and Application Processors
This paper provides an overview of the parallel architecture core (PAC) project led by SoC Technology Center of Industrial… 
2003
2003
An optical centralized shared-bus architecture demonstrator for microprocessor-to-memory interconnects
An architecture demonstrator of an innovative interconnect scheme called the optical centralized shared-bus is presented. This… 
2000
2000
Parallel Processor Configuration Design with Processing/Transmission Costs
A computer configuration design problem where the objective is to configure a parallel processor to do processing in a cost… 
1996
1996
RMB-a reconfigurable multiple bus network
The heart of a massively parallel computer is its interconnection network. In this article we present a reconfigurable multiple… 
1994
1994
Effect of fault tolerance and communication delay on response time in a multiprocessor system with a bus topology
1993
1993
Power distribution synthesis for analog and mixed-signal ASICs in RAIL
The authors present new power distribution synthesis techniques that can handle realistic analog and mixed-signal performance… 
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