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Bus network
Known as:
Bus topology
, Linear bus topology
A bus network is a network topology in which nodes are directly connected to a common linear (or branched) half-duplex link called a bus.
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Related topics
Related topics
18 relations
AppleTalk
Bus (computing)
Collision domain
DMX512
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Broader (2)
Network architecture
Network topology
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Enhanced Overloaded CDMA Interconnect (OCI) Bus Architecture for On-Chip Communication
K. E. Ahmed
,
Mohammed M. Farag
IEEE 23rd Annual Symposium on High-Performance…
2015
Corpus ID: 12444017
On-chip interconnect is a major building block and a main performance bottleneck in modern complex System-on-Chips (SoCs). The…
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2014
2014
Overloaded CDMA bus topology for MPSoC interconnect
K. E. Ahmed
,
Mohammed M. Farag
International Conference on Reconfigurable…
2014
Corpus ID: 5876173
Intra-chip communication is a major bottleneck in modern multiprocessor system-on-chip (MPSoC) designs. The bus topology is the…
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Review
2013
Review
2013
Pengembangan Array sensor Suhu dan Sistem Akusisi Data Berbasis Mikrokontroler untuk Pengukuran Suhu Bawah Permukaan
V. Suoth
,
D. Santoso
,
Sukir Maryanto
2013
Corpus ID: 109184528
Dalam penelitian ini dikembangkan sebuah sistem akusisi data untuk survei panas bumi. Untuk menghasilkan sistem instrumentasi…
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2011
2011
ISAC EPICS ON LINUX: THE MARCH OF THE PENGUINS
J. Richards
,
R. Nussbaumer
,
S. Rapaz
,
G. Waters
2011
Corpus ID: 55773107
The DC linear accelerators of the ISAC radioactive beam facility at TRIUMF do not impose rigorous timing constraints on the…
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2008
2008
MODELING FOR OPTIMIZATION OF URBAN TRANSIT SYSTEM UTILITY: A CASE STUDY
M. Muthukannan
,
A. M. Thirumurthy
2008
Corpus ID: 130693669
The model for optimization of transit system is developed by relating the demand of a mode to the aggregate cost of travel…
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2002
2002
Variable Mapping of System Level Design
Lukai Cai
,
D. Gajski
2002
Corpus ID: 11515663
This report presents a variable-memory mapping approach of the system level design, which maps the variables of the system…
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1997
1997
Financial information extraction using pre-defined and user-definable templates in the Lolita system
M. Constantino
1997
Corpus ID: 33811386
Financial operators have today access to an extremely large amount of data, both quantitative and qualitative, real-time or…
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1993
1993
Power distribution synthesis for analog and mixed-signal ASICs in RAIL
B. Stanisic
,
Rob A. Rutenbar
,
L. Carley
Proceedings of IEEE Custom Integrated Circuits…
1993
Corpus ID: 62325408
The authors present new power distribution synthesis techniques that can handle realistic analog and mixed-signal performance…
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1989
1989
A discrete-time approach to the modeling of carrier-sense multiple-access on the bus topology
A. Kamal
IEEE International Conference on Communications…
1989
Corpus ID: 2376839
An exact analysis of the carrier-sense multiple-access (CSMA) protocol on the bus topology is presented. All stations are…
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1977
1977
DECOMPOSITION APPROACH TO BUS NETWORK DESIGN
J. Hsu
,
V. H. Surti
1977
Corpus ID: 107913148
This paper presents a decomposition approach to bus network design in which the task of network design is accomplished through…
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