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Active redundancy
Active redundancy is a design concept that increases operational availability and that reduces operating cost by automating most critical maintenance…
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Related topics
Related topics
7 relations
AN/UYK-43
Artificial intelligence
Fault reporting
Operational availability
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Broader (2)
Fault tolerance
Reliability engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Active Redundancy in the Low Voltage Stage of Smart Transformers
V. Ferreira
,
Markus Andresen
,
B. Cardoso
,
Marco Liserre
European Conference on Cognitive Ergonomics
2018
Corpus ID: 54453377
The Smart Transformers (ST) enables the use of dc-grid and the voltage control of both low-voltage and medium-voltage (MV…
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2012
2012
Multi-objective optimization of a series-parallel system using GPSIA
E. Okafor
,
You-Chao Sun
Reliability Engineering & System Safety
2012
Corpus ID: 31668896
2012
2012
THE EFFECT OF ADDING COLD-STANDBY REDUNDANCY ON THE INCREASE OF SYSTEM RELIABILITY
A. Kadhem
2012
Corpus ID: 6091112
In this research, we study the effect of adding cold-standby redundancy in increasing system reliability. Cold-standby redundancy…
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2010
2010
Load allocation for risk management in overactuated systems experiencing incipient failure conditions
Brian Bole
,
Douglas W. Brown
,
Hailong Pei
,
K. Goebel
,
L. Tang
,
G. Vachtsevanos
Conference on Control and Fault Tolerant Systems
2010
Corpus ID: 34298389
This paper examines the fault tolerant control problem for a generic class of incipient failure modes that grow in severity as a…
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2008
2008
Integrating safety and multimedia subsystems on a Time-Triggered System-on-a-Chip
R. Obermaisser
,
B. Fromel
,
C. El Salloum
,
B. Huber
6th IEEE International Conference on Industrial…
2008
Corpus ID: 15340730
The time-triggered system-on-a-chip (TTSoC) architecture enables the realization of mixed-criticality systems using SoCs. The…
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2008
2008
A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR
R. Obermaisser
,
H. Kraut
,
C. E. Salloum
Seventh European Dependable Computing Conference
2008
Corpus ID: 7037229
The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive…
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2007
2007
End-to-End Delays of Event-Triggered Overlay Networks in a Time-Triggered Architecture
R. Obermaisser
5th IEEE International Conference on Industrial…
2007
Corpus ID: 12788646
Event-triggered overlay networks are a solution for extending time-triggered networks with support for additional event-triggered…
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1998
1998
Optimal design of systems using active redundancy with repairable components
D. Ait-kadi
,
A. Chelbi
1998
Corpus ID: 125229887
This paper deals with the problem of the optimization of industrial systems availability using active redundancy with repairable…
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1993
1993
A Functional and Attribute Based Computational Model for Fault-Tolerant Software
Masato Suzuki
,
T. Katayama
,
R. Schlichting
1993
Corpus ID: 15305278
Programs constructed using techniques that allow software or operational faults to be tolerated are typically written using an…
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1993
1993
Redundancy management in the SCEPTRE2 real-time executive
S. Bestaoui
,
A. Déplanche
,
Y. Trnquet
IEEE International Conference on Systems, Man and…
1993
Corpus ID: 62250564
SCEPTRE2 is a normative report on the basic mechanisms of the real-time executive kernels. No fault tolerance technique exists in…
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