Multiple observation time single reference test generation using synchronizing sequences

@article{Cho1993MultipleOT,
  title={Multiple observation time single reference test generation using synchronizing sequences},
  author={Hyunwoo Cho and S.-W. Jeong and F. Somenzi and Carl Pixley},
  journal={1993 European Conference on Design Automation with the European Event in ASIC Design},
  year={1993},
  pages={494-498},
  url={https://api.semanticscholar.org/CorpusID:62237269}
}
  • Hyunwoo ChoS.-W. Jeong C. Pixley
  • Published in European Conference on Design… 22 February 1993
  • Engineering, Computer Science
  • 1993 European Conference on Design Automation with the European Event in ASIC Design
It is shown that the same fault coverage can be achieved in both tester operation models if the circuit under test generation is synchronizable and the authors investigate how a synchronizing sequence simplifies test generation and allows one to use the simpler testeroperation model.
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    Computer Science, Engineering
    Proceedings of the European Conference on Design…
  • 1991
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