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posterior lateral line system development

Known as: PLL 
The process whose specific outcome is the progression of the posterior lateral line system over time, from its formation to the mature structure. The… (More)

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1974-2018
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posterior lateral line development

Related mentions per year

Related mentions per year

1974-2018
197019801990200020102020
posterior lateral line system development
posterior lateral line development

Papers overview

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Highly Cited
2008
Highly Cited
2008
A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI
An all static CMOS ADPLL fabricated in 65 nm digital CMOS SOI technology has a fully programmable proportional-integral… (More)
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Highly Cited
2007
Highly Cited
2007
Decoupled Double Synchronous Reference Frame PLL for Power Converters Control
This paper deals with a crucial aspect in the control of grid-connected power converters, i.e., the detection of the fundamental… (More)
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Highly Cited
2005
Highly Cited
2005
All-digital PLL and transmitter for mobile phones
We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver… (More)
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Highly Cited
2004
Highly Cited
2004
A wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s in-loop modulation
A phase noise cancellation technique and a charge pump linearization technique, both of which are insensitive to component errors… (More)
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Highly Cited
2004
Highly Cited
2004
Performance evaluation of PLL algorithms for single-phase grid-connected systems
Phase angle, frequency and amplitude of the utility voltage vector are basic information for an increasing number of grid… (More)
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Highly Cited
2003
Highly Cited
2003
Characterization of biophysical and metabolic properties of cells labeled with superparamagnetic iron oxide nanoparticles and transfection agent for cellular MR imaging.
PURPOSE To evaluate the effect of using the ferumoxides-poly-l-lysine (PLL) complex for magnetic cell labeling on the long-term… (More)
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Highly Cited
2001
Highly Cited
2001
A 1.75 GHz highly-integrated narrow-band CMOS transmitter with harmonic-rejection mixers
A 1.75 GHz transmitter with harmonic and double image reject mixer integrates the full signal path from the DAC to the RF output… (More)
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Highly Cited
2001
Highly Cited
2001
PLL structures for utility connected systems
This paper presents a detailed analysis of PLL structures for utility connected systems. The three-phase PLL (phase-locked loop… (More)
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Highly Cited
2001
Highly Cited
2001
A Modeling Approach for – Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis
A general model of phase-locked loops (PLLs) is derived which incorporates the influence of divide value variations. The proposed… (More)
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Highly Cited
1996
Highly Cited
1996
Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques
Delay-locked loop (DLL) and phase-locked loop (PLL) designs based upon self-biased techniques are presented. The DLL and PLL… (More)
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