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Verilog
Known as:
IEEE 1364
, .v
, Verilog 95
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Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design…
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Related topics
Related topics
50 relations
ARM architecture
Application-specific integrated circuit
Atmel AVR
Bit array
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Wavelength Assignment for Physical-Layer-Impaired Optical Networks Using Evolutionary Computation
C. Bastos-Filho
,
D. Chaves
,
Felipe S. F. e Silva
,
Helder A. Pereira
,
J. Martins-Filho
IEEE\/OSA Journal of Optical Communications and…
2011
Corpus ID: 18713299
This paper presents a wavelength assignment algorithm suitable for optical networks mainly impaired by physical layer effects…
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2010
2010
On The Impact of Target Technology in SHA-3 Hardware Benchmark Rankings
Xu Guo
,
Si-Nan Huang
,
Leyla Nazhandali
,
P. Schaumont
IACR Cryptology ePrint Archive
2010
Corpus ID: 14465778
Both FPGAs and ASICs are widely used as the technology for comparing SHA-3 hardware benchmarking process. However, the im- pact…
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2010
2010
FSSA: Fast Steady-State Algorithm for the Analysis of Mixed Analog/Digital Circuits
A. Brambilla
,
G. Gruosso
,
G. S. Gajani
IEEE Transactions on Computer-Aided Design of…
2010
Corpus ID: 9462493
The shooting method is largely employed to determine the steady-state working condition of both autonomous and nonautonomous…
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2007
2007
NISAR: An AXI compliant on-chip NI architecture offering transaction reordering processing
Xu Yang
,
Zhang Qing-li
,
Fu Fang-fa
,
Yu Ming-yan
,
Liu-Fang Cheng
International Conference on ASIC
2007
Corpus ID: 36813091
In this paper, we present an AXI compliant Network Interface (NI) for NoC, which can deal with the reordering problem and support…
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2005
2005
Models of Embedded Computation
A. Jantsch
Embedded Systems Handbook
2005
Corpus ID: 1648940
Axel Jantsch Royal Institute of Technology 4.
2000
2000
Multiclock Esterel: a reactive framework for asynchronous design
B. Rajan
,
R. Shyamasundar
Proceedings, International Parallel and…
2000
Corpus ID: 896756
In this paper, we discuss a new paradigm called Multiclock Esterel, based on the paradigm of the synchronous reactive language…
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1999
1999
Reconfigurable Multiplier for Virtex FPGA Family
Juri Põldre
,
Kalle Tammemäe
International Conference on Field-Programmable…
1999
Corpus ID: 206727281
This paper describes integer multiplier design optimizations for FPGA technology. The changes in partial product generator…
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1998
1998
Plastic cell architecture: towards reconfigurable computing for general-purpose
Kouichi Nagami
,
K. Oguri
,
T. Shiozawa
,
H. Ito
,
Ryusuke Konishi
Proceedings. IEEE Symposium on FPGAs for Custom…
1998
Corpus ID: 5997531
We propose a new architectural reference based on programmable logic devices that we call Plastic Cell Architecture (PCA). PCA is…
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Highly Cited
1998
Highly Cited
1998
Verilog HDL Synthesis, A Practical Primer
J. Bhasker
1998
Corpus ID: 60077791
From the Publisher: With this book, you can: Start writing synthesizable Verilog models quickly. See what constructs are…
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Review
1993
Review
1993
Timber plantations in the humid tropics of Africa
B. Dupuy
,
G. Mille
1993
Corpus ID: 127232060
Historical Survey Recent Techniques and Orientations - Reforestation in Cleared Areas Silvicultural Rules for the Principal…
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