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Transistor count
Known as:
List of integrated circuits by number of transistors
The transistor count is the number of transistors on an integrated circuit (IC). Transistor count is the most common measure of IC complexity…
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AMD K5
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AND gate
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Analysis of energy efficient PTL based full adders using different nanometer technologies
Deepa
,
V. Kumar
International Conference on Electronics, Circuits…
2015
Corpus ID: 26156837
Full adder can be designed using CMOS logic, transmission gates, dynamic logic or pass transistor logic. This paper presents Pass…
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2014
2014
Power and Stability Analysis of a Proposed 12T MTCMOS SRAM Cell for Low Power Devices
P. Upadhyay
,
N. Agarwal
,
R. Kar
,
D. Mandal
,
S. Ghoshal
Fourth International Conference on Advanced…
2014
Corpus ID: 5782423
This paper focuses on the power dissipations at different temperatures and stability analysis at different pull-up ratios of a…
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2013
2013
Impact of Transistor Architecture (Bulk Planar, Trigate on Bulk, Ultrathin-Body Planar SOI) and Material (Silicon or III–V Semiconductor) on Variation for Logic and SRAM Applications
N. Agrawal
,
Y. Kimura
,
R. Arghavani
,
S. Datta
IEEE Transactions on Electron Devices
2013
Corpus ID: 2394450
The need to enhance transistor performance below 22-nm node has brought in a change in transistor architecture from planar bulk…
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2013
2013
Designing function configuration decoders for the PAnDA architecture using multi-objective Cartesian Genetic Programming
James Alfred Walker
,
M. Trefzer
,
A. Tyrrell
International Conference on Evolvable Systems
2013
Corpus ID: 7046648
The Programmable Analogue and Digital Array (PAnDA) is a novel reconfigurable architecture, which allows variability aware design…
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2011
2011
A semi-static threshold-triggered delay element for low power applications
L. H. Jung
,
T. Lehmann
,
G. Suaning
,
N. Lovell
International Symposium on Circuits and Systems
2011
Corpus ID: 206970523
Delay elements are used in integrated circuits (ICs) to meet design specific timing requirements. Delays are often generated by…
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2010
2010
Current Mode Image Sensor With Two Transistors per Pixel
V. Gruev
,
Zheng Yang
,
J. Spiegel
,
R. Etienne-Cummings
IEEE Transactions on Circuits and Systems Part 1…
2010
Corpus ID: 8410242
A linear current mode active pixel sensor for low fixed-pattern noise imaging is presented. The photo pixel is composed of a…
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2009
2009
An Area and Power Efficient Design of Single Edge Triggered D-Flip Flop
Manoj Sharma
,
A. Noor
,
S. Tiwari
,
Kunwar Singh
International Conference on Advances in Recent…
2009
Corpus ID: 16313906
In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed…
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2003
2003
High fan-in dynamic CMOS comparators with low transistor count
Chua-Chin Wang
,
Po-Ming Lee
,
Chi-Feng Wu
,
Hsin-Long Wu
2003
Corpus ID: 62242463
In this work, we propose several high fan-in dynamic CMOS comparators with low transistor count, high speed and low power. Major…
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2001
2001
Memory and logic integration for System-in-a-Package
M. Wang
,
K. Suzuki
,
A. Sakai
,
W. Dai
ASICON . 4th International Conference on ASIC…
2001
Corpus ID: 9336016
System-in-a-Package (SiP), a generalization of System-on-a-Chip (SoC), provides a cost-effective solution for large-scale memory…
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Highly Cited
1997
Highly Cited
1997
A Reduced Clock-swing Flip-flop (RCSFF) For 63% Clock Power Reduction
Hiroshi Kawaguchi
,
Takayasu Sakurai
Symposium on VLSI Circuits
1997
Corpus ID: 30583683
A reduced clock-swing flip-flop (RCSFF) is proposed, which is composed of a reduced swing clock driver and a special flip-flop…
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