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Spurious-free dynamic range
Known as:
SFDR
Spurious-free dynamic range (SFDR) is the strength ratio of the fundamental signal to the strongest spurious signal in the output. Itis also defined…
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Related topics
Related topics
15 relations
Analog-to-digital converter
Bandwidth (signal processing)
Carrier wave
Digital-to-analog converter
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Broader (1)
Digital signal processing
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Spurious-Free Dynamic Range of CORDIC Based Digital Quadrature Demodulator
P. Puzyrev
,
K. V. Semenov
,
S. Zavyalov
Educational Data Mining
2018
Corpus ID: 52019895
This paper presents research of influence of CORDIC algorithm parameters on the single tone spurious free dynamic range (SFDR…
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2017
2017
Spurious-Free Dynamic Range of the Photonic Time-Stretch System
Yuan Mei
,
Yuxiao Xu
,
+4 authors
Xianmin Zhang
IEEE Photonics Technology Letters
2017
Corpus ID: 19883503
Analog-to-digital conversion based on photonic time-stretch (PTS) has been widely studied. The performance of PTS systems is…
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Highly Cited
2011
Highly Cited
2011
Optically Filtered Microwave Photonic Links for RF Signal Processing Applications
A. Agarwal
,
T. Banwell
,
T. K. Woodward
Journal of Lightwave Technology
2011
Corpus ID: 23047265
The performance of filtered analog photonic links, useful in signal processing applications, is analyzed along with techniques…
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2009
2009
A highly reconfigurable 400–1700MHz receiver using a down-converting sigma-delta A/D with 59-dB SNR and 57-dB SFDR over 4-MHz bandwidth
Renaldi Winoto
,
B. Nikolić
Symposium on VLSI Circuits
2009
Corpus ID: 18808079
A highly reconfigurable radio-frequency-to-digital signal converter is presented. Center frequency is precisely defined by a…
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Highly Cited
2008
Highly Cited
2008
An 11-Bit 45 MS/s Pipelined ADC With Rapid Calibration of DAC Errors in a Multibit Pipeline Stage
I. Ahmed
,
D. Johns
IEEE Journal of Solid-State Circuits
2008
Corpus ID: 6288179
A technique to rapidly correct for both DAC and gain errors in the multibit first stage of an 11-bit pipelined ADC is presented…
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Highly Cited
2007
Highly Cited
2007
A Low-Noise 40-GS/s Continuous-Time Bandpass $\Delta\Sigma$ ADC Centered at 2 GHz for Direct Sampling Receivers
T. Chalvatzis
,
E. Gagnon
,
Morris Repeta
,
S. Voinigescu
IEEE Journal of Solid-State Circuits
2007
Corpus ID: 642832
This paper presents a 40-GS/s continuous-time bandpass DeltaSigma analog-to-digital converter centered at 2 GHz for wireless base…
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2006
2006
Revisiting spurious-free dynamic range of communication receivers
J. Lerdworatawee
,
W. Namgoong
IEEE Transactions on Circuits and Systems Part 1…
2006
Corpus ID: 14745764
The spurious free dynamic range (SFDR) is commonly used as a measure of dynamic range for the radio frequency and microwave front…
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2005
2005
Wide-bandwidth, vector-corrected measurement with high spurious-free dynamic range
P. Blockley
,
D. Gunyan
,
J.B. Scott
65th ARFTG Conference Digest, . Spring
2005
Corpus ID: 19896790
Wide-bandwidth vector-signal measurements with high spurious-free dynamic range (SFDR), are difficult to make with traditional…
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2004
2004
A 14-bit delta-sigma ADC with 8/spl times/ OSR and 4-MHz conversion bandwidth in a 0.18-/spl mu/m CMOS process
Ruoxin Jiang
,
T. Fiez
IEEE Journal of Solid-State Circuits
2004
Corpus ID: 890362
A 14-bit 8/spl times/ oversampling delta-sigma (/spl Delta//spl Sigma/) analog-to-digital converter (ADC) for wide-band…
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2001
2001
A 14 b 40 MSample/s pipelined ADC with DFCA
Paul Yu
,
Shereef Shehata
,
+6 authors
Turker Kuyel
IEEE International Solid-State Circuits…
2001
Corpus ID: 10476280
A DAC and feedback capacitor averaging (DFCA) technique used in a pipelined ADC achieves 84 dB SFDR and 74 dB SNR. Also external…
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