Skip to search formSkip to main contentSkip to account menu

Software verification

Known as: Verification 
Software verification is a discipline of software engineering whose goal is to assure that software fully satisfies all the expected requirements… 
Wikipedia (opens in a new tab)

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Dewasa ini peran internet bukan hanya sebagai sarana mencari informasi, tapi juga mempunyai potensi besar sebagai media pemasaran… 
2010
2010
We describe the first software tool for the verification of TinyOS 2, MSP430 applications at compile-time. Given assertions upon… 
2010
2010
Access control mechanisms are a widely adopted technology for information security. Since access decisions (i.e., permit or deny… 
2007
2007
Verification engineers cannot guarantee the correctness of the system implementation by model checking if the set of proven… 
2007
2007
The problem of supporting the secure execution of potentially malicious third-party applications has received a considerable… 
2006
2006
Transit planners need cost-effective ways to evaluate a wide range of alternatives relatively quickly to identify potential… 
2006
2006
Programmable logic controllers (PLCs) occupy a big share in automation control. Their programming languages are, however, born… 
Highly Cited
2005
Highly Cited
2005
We describe a toolbox for the analysis of systems-on-a-chip described in SystemC at the transactional level. The tools are able… 
Review
1996
Review
1996
This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and… 
1986
1986
Three effects appear to influence the yield of digital memory chips. In the first effect, yields appear to decrease faster with…