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Software Upgrade Protocol
Known as:
SUP
The Software Upgrade Protocol (or SUP) System is a set of programs developed by Carnegie Mellon University in the 1980s (as was the Andrew File…
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Review
2002
Review
2002
The SUP 35 Omnipotent Suppressor Gene Is Involved in the Maintenance of the Non-Mendelian Determinant [ psi ' ] in the Yeast Saccharomyces cerevisiae
M. Ter‐Avanesyan
,
A. R. Dagkesamanskaya
,
V. Kushnirov
,
V. Smirnov
2002
Corpus ID: 45650950
The SUP35 gene of yeast Saccharomyces cerevisiae encodes a 76.5-kD ribosome-associated protein (Sup35p), the Gterminal part of…
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1987
1987
A million-cycle CMOS 256 K EEPROM
D. Cioaca
,
Tien Lin
,
A. Chan
,
L. Chen
,
A. Mihnea
1987
Corpus ID: 62657264
A single 5-V supply 256 K EEPROM (electrically erasable programmable read-only memory) was designed, manufactured, and tested. A…
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Highly Cited
1985
Highly Cited
1985
An 8-kbit content-addressable and reentrant memory
Hiroshi
,
Kadota
,
Jiro Miyake
,
Hitoshi
,
Kudoh
IEEE Journal of Solid-State Circuits
1985
Corpus ID: 34741745
A 256-word/spl times/32-bit associated memory, referred to as the Content Addressable and Reentrant Memory (CARM), with a 100-ns…
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Highly Cited
1981
Highly Cited
1981
A high-frequency temperature-stable monolithic VCO
J. F. Kukielka
,
R. Meyer
IEEE Journal of Solid-State Circuits
1981
Corpus ID: 10058177
A new high-frequency monolithic voltage-controlled oscillator (VCO) is described that achieves /spl plusmn/60 ppm//spl deg/C…
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1977
1977
Second generation I/sup 2/L/MTL: a 20 ns process/structure
J. M. Herman
,
S. A. Evans
,
B. Sloan
IEEE Journal of Solid-State Circuits
1977
Corpus ID: 22491927
A high performance, second generation I/SUP 2/L/MTL gate for digital LSI applications with TTL compatibility has successfully…
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Highly Cited
1977
Highly Cited
1977
Threshold I/sup 2/L and its applications to binary symmetric functions and multivalued logic
T. T. Dao
IEEE Journal of Solid-State Circuits
1977
Corpus ID: 32663951
I/SUP 2/L threshold gate using current mirrors providing weighting of inputs, summation, and comparison with a threshold is…
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1976
1976
High speed integrated injection logic (I/sup 2/L)
C. Mulder
,
H. Wulms
IEEE Journal of Solid-State Circuits
1976
Corpus ID: 9941581
High speed integrated injection logic (I/SUP 2/L) circuits can be manufactured in a process using oxide separation involving a…
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1974
1974
Integrated injection logic-present and future
N. C. D. Troye
1974
Corpus ID: 62599412
Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current…
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Highly Cited
1972
Highly Cited
1972
Integrated injection logic: a new approach to LSI
C. M. Hart
,
A. Slob
1972
Corpus ID: 62625941
Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used…
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Highly Cited
1972
Highly Cited
1972
Merged-transistor logic (MTL)-a low-cost bipolar logic concept
H. Berger
,
S. Wiedmann
1972
Corpus ID: 61494943
The authors describe a novel bipolar logic featuring a direct injection of minority carriers into the switching transistor. MTL…
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