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Register window

Known as: Window (disambiguation) 
In computer engineering, register windows are a feature in some instruction set architectures to improve the performance of procedure calls, a very… Expand
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Related topics

Related topics

22 relations
AMD Am29000Berkeley RISCCalling conventionCentral processing unit
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors
Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development… Expand
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2005
2005
Partitioning variables across register windows to reduce spill code in a low-power processor
Low-power embedded processors utilize compact instruction encodings to achieve small code size. Such encodings place tight… Expand
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2003
2003
Early Control of Register Pressure for Software Pipelined Loops
The register allocation in loops is generally performed after or during the software pipelining process. This is because doing a… Expand
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2000
2000
Power and Control in Networked Sensors
The fundamental constraint on a networked sensor is its energy consumption, since it may be either impossible or not feasible to… Expand
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2000
2000
Register queues: a new hardware/software approach to efficient software pipelining
In this paper we propose a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected… Expand
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Highly Cited
1994
Highly Cited
1994
Quantifying Behavioral Differences Between C and C++ Programs
Improving the performance of C programs has been a topic of great interest for many years. Both hardware technology and compiler… Expand
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Highly Cited
1992
Highly Cited
1992
Register allocation for software pipelined loops
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops… Expand
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Highly Cited
1990
Highly Cited
1990
APRIL: a processor architecture for multiprocessing
Processors in large-scale multiprocessors must be able to tolerate large communication latencies and synchronization delays. This… Expand
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1990
1990
Architectural support for register allocation in the presence of aliasing
A hardware support mechanism is presented that permits all classes of data objects, including dynamically allocated objects and… Expand
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1987
1987
A performance analysis of automatically managed top of stack buffers
In this paper, the feasibility of using register banks as a top of stack (TOS) buffer is demonstrated. A quantitative performance… Expand
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