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Register window

Known as: Window (disambiguation) 
In computer engineering, register windows are a feature in some instruction set architectures to improve the performance of procedure calls, a very… 
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22 relations
AMD Am29000Berkeley RISCCalling conventionCentral processing unit

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Yield maximization for system-level task assignment and configuration selection of configurable multiprocessors
Configurable multiprocessor system is a promising design alternative because of its high degree of flexibility, short development… 
2005
2005
Reducing instruction fetch cost by packing instructions into register windows
Instruction packing is a combination compiler/architectural approach that allows for decreased code size, reduced power… 
2002
2002
Exploring the number of register windows in ASIP synthesis
ASIPs (Application Specific Instruction Set Processors) are one of the key components of many embedded systems which are… 
2000
2000
Power and Control in Networked Sensors
The fundamental constraint on a networked sensor is its energy consumption, since it may be either impossible or not feasible to… 
2000
2000
Register queues: a new hardware/software approach to efficient software pipelining
In this paper we propose a new hardware mechanism, called Register Queues (RQs), which effectively decouples the architected… 
1992
1992
Pseudo vector processor based on register-windowed superscalar pipeline
The authors present a novel architecture for a high-speed pseudo vector processor based on a superscalar pipeline. Without using… 
1990
1990
Evaluation of the optimal strategy for managing the register file
1990
1990
Reconfigurable vector register windows for fast matrix computation on the orthogonal multiprocessor
  • D. PandaK. Hwang
  • [] Proceedings of the International Conference on…
  • 1990
  • Corpus ID: 62760421
The authors present the concept of vector register windows (VRWs) geared towards large scale matrix computation and image… 
1988
1988
The architecture of RIG: A RISC for image generation in a multi-microprocessor environment
1987
1987
A performance analysis of automatically managed top of stack buffers
In this paper, the feasibility of using register banks as a top of stack (TOS) buffer is demonstrated. A quantitative performance… 
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