Skip to search formSkip to main contentSkip to account menu

RLC circuit

Known as: RLC circuits, RCL circuit, LCR circuit 
An RLC circuit is an electrical circuit consisting of a resistor (R), an inductor (L), and a capacitor (C), connected in series or in parallel. The… 
Wikipedia (opens in a new tab)

Related topics

Related topics

32 relations
Analog signal processingAnalogue filterBandwidth (signal processing)Crystal oscillator

Broader (1)

Electronic filter topology

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2014
Highly Cited
2014
An Accurate FDTD Model for Crosstalk Analysis of CMOS-Gate-Driven Coupled RLC Interconnects
This paper accurately models the crosstalk effects in a CMOS-gate-driven coupled RLC interconnects using the nth power law model… 
Highly Cited
2004
Highly Cited
2004
A CMOS impulse generator for UWB wireless communication systems
A fully integrated CMOS impulse generator was designed as a part of the System-on-Chip (SOC) implementation of an Ultra-Wide… 
Highly Cited
2003
Highly Cited
2003
User satisfaction models and scheduling algorithms for packet-switched services in UMTS
In this paper, we propose a user satisfaction model for packet-switched services in next generation wireless networks for… 
Highly Cited
2001
Highly Cited
2001
Broadband wireless access and future communication networks
This paper presents a vision for wireless communication systems beyond the third generation, which comprises a combination of… 
Highly Cited
2000
Highly Cited
2000
Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization
In this paper, we first show that existing net ordering formulations to minimize noise are no longer valid with presence of… 
1996
1996
Efficient gate delay modeling for large interconnect loads
  • A. KahngS. Muddu
  • Proceedings IEEE Multi-Chip Module Conference…
  • 1996
  • Corpus ID: 2613896
With fast switching speeds and large interconnect trees (MCMs), the resistance and inductance of interconnect has a dominant… 
Highly Cited
1996
Highly Cited
1996
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models
  • Qing K. ZhuW. Dai
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1996
  • Corpus ID: 37566492
To achieve path delay balance, instead of making faster paths slower by elongating wires used in most zero skew clock routing… 
Highly Cited
1993
Highly Cited
1993
High frequency compensated current-mode ladder filters using multiple output OTAs
A methodology to synthesize continuous-time current-mode filters using multiple output operational transconductance amplifiers… 
Highly Cited
1968
Highly Cited
1968
An approach to the implementation of digital filters
An approach to the implementation of digital filters is presented that employs a small set of relatively simple digital circuits… 
1968
1968
IF Amplifier using C/SUB c/ compensated transistors
An integrated bridge network of four transistors is used as a self-neutralized active element in tuned RLC amplifier designs. The… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)