Skip to search formSkip to main contentSkip to account menu

Pre-charge

Pre-charge of the powerline voltages in a high voltage DC application is a preliminary mode which current-limits the power source such that a… 
Wikipedia (opens in a new tab)

Related topics

Related topics

4 relations

Broader (2)

Electrical engineeringElectronic engineering
Hot swappingRelay

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
Predictive transient circuit simulations of charged device model ESD events in system in package chips
2013
2013
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs
Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper… 
2011
2011
Choosing Distinguishers for Di erential Power Analysis Attacks
Di erential power analysis attacks are among the `classical' non-invasive types of attacks against physical devices. Attacks… 
2010
2010
Virtual Secure Circuit: Porting Dual-Rail Pre-charge Technique into Software on Multicore
This paper discusses a novel direction for multicore cryptographic software, namely the use of multicore to protect a design… 
2008
2008
CHARACTERIZATION OF A DC/DC CONVERTER USING AN IN-PLANE BULK SILICON CAPACITIVE TRANSDUCER FOR VIBRATION-TO- ELECTRICITY POWER CONVERSION
In this work, we have successfully implemented an electrostatic transducer in a charge-pump circuit for harvesting the energy… 
2007
2007
The sliding voltage control strategy for power peaks bypass
The variable speed generating units have not enough power reserve for rapid load step-up, when they are operated at low speed… 
2006
2006
A Switched-Active and Passive Filter Configuration for Resonance-Free Transient Regulation
The transient-induced resonance on the output voltage of a power supply can be eliminated if the output filter of the power… 
2005
2005
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning
A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy… 
1996
1996
On The Design of Adiabatic SRAMs
In the design of low-power circuits, adiabatic logic shows great promise. However, research till date have concentrated on… 
1987
1987
GRADUATION: SOME EXPERIMENTS WITH KERNEL METHODS
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)