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Pre-charge

Pre-charge of the powerline voltages in a high voltage DC application is a preliminary mode which current-limits the power source such that a… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
An all-n-type dynamic adder for ultra-low-leakage IoT devices
Ultra-low leakage is demanded for low-duty-cycled IoT applications. An NP-type dynamic ripple-carry adder (NP-RCA) was shown… 
2016
2016
Feature Indented Assertions for Analog and Mixed-Signal Validation
The acceptance criteria for analog designs are traditionally defined in terms of real-valued features defined over behavioral… 
2016
2016
New Start-Up Scheme for HF Transformer Link Photovoltaic Inverter
Safe start-up procedure is critical for the reliable operation of power converters. The challenges in start-up schemes of high… 
2013
2013
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs
Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper… 
2012
2012
Reliability of SRAMs and 3D TSV ICS: Design Protection from Soft Errors and 3D Thermal Modeling
2012
2012
Design and simulation of a DC electric vehicle charging station connected to a MVDC infrastructure
Medium Voltage DC (MVDC) infrastructure serves as a platform for interconnecting renewable electric power generation, including… 
2009
2009
A Trust Based Cross Layer Security Protocol for Mobile Ad hoc Networks
In this paper, we develop a trust based security protocol based on a cross layer approach which attains confidentiality and… 
2009
2009
Design and Validation of a High Energy Density Elastic Accumulator Using Polyurethane
Hydraulic accumulators (HAs) have been used successfully in regenerative braking systems by companies such as Ford and Eaton Corp… 
2009
2009
Cooling process of pre-combustion residual gases in the Eindhoven high pressure cell
In this paper we analyze the cooling process that is initiated by combustion in a closed cell. This is important for experimental… 
2005
2005
A 322 MHz random-cycle embedded DRAM with high-accuracy sensing and tuning
A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy… 
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