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Parity bit
Known as:
Parity code
, Parity checking
, Parity
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A parity bit, or check bit, is a bit added to a string of binary code that indicates whether the number of 1-bits in the string is even or odd…
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Related topics
Related topics
49 relations
8-bit clean
Apollo Guidance Computer
BIP-8
Bi-quinary coded decimal
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Broader (2)
Error detection and correction
RAID
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Asymptotic structure of N=2$$ \mathcal{N}=2 $$ supergravity in 3D: extended super-BMS3 and nonlinear energy bounds
Oscar Fuentealba
,
Javier Matulich
,
Ricardo Troncoso
2017
Corpus ID: 119211534
A bstractThe asymptotically flat structure of N=20$$ \mathcal{N}=\left(2,0\right) $$ supergravity in three spacetime dimensions…
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Review
2016
Review
2016
Min-Max decoding for non binary LDPC codes
Danfeng Zhao
,
Jiahui Meng
,
Hai Tian
2016
Corpus ID: 63441673
with the increase in requirements on fiber-optical communication system by people, transmission quantity has been increased. In…
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Highly Cited
2012
Highly Cited
2012
NEW CONSTRAINTS ON THE GALACTIC HALO MAGNETIC FIELD USING ROTATION MEASURES OF EXTRAGALACTIC SOURCES TOWARD THE OUTER GALAXY
S. A. Mao
,
N. McClure-Griffiths
,
+7 authors
A. Taylor
2012
Corpus ID: 40375981
We present a study of the Milky Way disk and halo magnetic field, determined from observations of Faraday rotation measure (RM…
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2004
2004
Blind recognition of punctured convolutional codes
Peizhong Lu
,
Shen Li
,
Yan Zou
,
Xiangyang Luo
International Symposium onInformation Theory…
2004
Corpus ID: 26430580
This paper presents an algorithm for blind recognition of punctured convolutional codes which is an important problem in adaptive…
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2001
2001
The /spl pi/-rotation low-density parity check codes
R. Echard
,
Shih-Chun Chang
GLOBECOM'01. IEEE Global Telecommunications…
2001
Corpus ID: 12279850
We introduce an ensemble of quasi-regular low-density parity check error control codes we call /spl pi/-rotation LDPC codes…
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2001
2001
1 GHz HAL SPARC64/sup R/ Dual Floating Point Unit with RAS features
A. Naini
,
Atul Dhablania
,
Warren James
,
Debjit Das Sarma
Proceedings 15th IEEE Symposium on Computer…
2001
Corpus ID: 29098624
An IEEE compliant, 1 GHz Sparc64-V Floating-Point Unit (FPU) with reliability-accessibility-serviceability (RAS) features and…
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Review
2000
Review
2000
Implementation of near Shannon limit error-correcting codes using reconfigurable hardware
B. Levine
,
R. Taylor
,
H. Schmit
Proceedings IEEE Symposium on Field-Programmable…
2000
Corpus ID: 6355131
Error correcting codes (ECCs) are widely used in digital communications. New types of ECCs have been proposed which permit error…
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1987
1987
Selector-line merged built-in ECC technique for DRAMs
J. Yamada
1987
Corpus ID: 62147697
A high-performance built-in error checking and correcting (ECC) technique applicable to megabit-level dynamic RAM (DRAM) chips is…
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1983
1983
Differential PSK System with Nonredundant Error Correction
S. Samejima
,
K. Enomoto
,
Yoshio Watanabe
IEEE J. Sel. Areas Commun.
1983
Corpus ID: 30038566
Theoretical analysis and experimental results for a DPSK system with nonredundant error correction are described. The error…
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Highly Cited
1956
Highly Cited
1956
A note off two binary signaling alphabets
D. Slepian
IRE Transactions on Information Theory
1956
Corpus ID: 5095214
A generalization of Hamming's single error correcting codes is given along with a simple maximum likelihood detection scheme. For…
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