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POWER5
Known as:
POWER5+
The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for…
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ASC Purple
Apache Nutch
Central processing unit
Comparison of platform virtualization software
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Papers overview
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2013
2013
Science at LLNL with IBM Blue Gene/Q
B. Carnes
,
B. Chan
,
+21 authors
Hui-Fang Wen
IBM Journal of Research and Development
2013
Corpus ID: 207677126
Lawrence Livermore National Laboratory (LLNL) has a long history of working with IBM on Blue Gene® supercomputers. Beginning in…
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2010
2010
Many Task Computing for modeling the fate of oil discharged from the Deep Water Horizon well blowout
A. Srinivasan
,
M. Hénaff
,
+8 authors
O. Knio
3rd Workshop on Many-Task Computing on Grids and…
2010
Corpus ID: 10559476
The Deep Water Horizon well blowout on April 20th 2010 discharged between 40,000–1.2 million tons of crude oil into the Gulf of…
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2009
2009
Using Large Page and Processor Binding to Optimize the Performance of OpenMP Scientific Applications on an IBM POWER 5 + System
Xingfu Wu
,
V. Taylor
2009
Corpus ID: 9631458
Multicores are widely used for high performance computing and are being configured in a hierarchical manner to compose a…
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2008
2008
Performance Comparison of Cray XT4 with SGI Altix 4700, IBM POWER5+, SGI ICE 8200, and NEC SX-8 using HPCC and NPB Benchmarks
Subash Saini
,
Dale Talcott
,
R. Rabenseifner
,
Michael Schliephake
,
K. Benkert
2008
Corpus ID: 60047529
Performance Comparison of Cray XT4 with SGI Altix 4700, IBM POWER5+, SGI ICE 8200, and NEC SX-8 using HPCC and NPB Benchmarks
2008
2008
Implementation of Integer Multiplication in Multiple-Precision on POWER5+ Architecture
T. Hirota
,
H. Kuroda
International Conference on Scientific Computing
2008
Corpus ID: 45579457
A raceway for a curved wall panel, which raceway is formed by two substantially identical raceway cover members which are of…
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2008
2008
Array optimizations for parallel implementations of high productivity languages
Mackale Joyner
,
Zoran Budimlic
,
Vivek Sarkar
,
Rui Zhang
IEEE International Symposium on Parallel and…
2008
Corpus ID: 18779411
This paper presents an interprocedural rank analysis algorithm to automatically infer ranks of arrays in X10, a language that…
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Review
2006
Review
2006
HPC Integer Benchmarks : An Indepth Analysis of the Performance Sensitivity of Legacy codes on Current Hardware Platforms
C. Kitchen
,
M. Guest
,
M. Ehrig
,
M. Deegan
,
I. Kozin
,
R. Wain
2006
Corpus ID: 17108600
This paper presents a performance analysis of an HPC Integer Benchmark comprising seven legacy codes (and 13 associated data sets…
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2006
2006
The IBM Power Micro-architecture Report for COMP9244: Software View of Processor Architectures
G. Linden
2006
Corpus ID: 5622707
The IBM PowerPC instruction set architecture and the implementations of it have powered many dierent computer systems. It is a…
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2006
2006
Is Cache Oblivious DGEMM a Viable Alternative ?
K. Yotov
,
T. Roeder
,
K. Pingali
,
J. Gunnels
,
F. Gustavson
2006
Corpus ID: 16276418
We present an in-depth study of various implementations of DGEMM, using both the recursive and iterative programming styles…
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Review
2003
Review
2003
IBM Previews Power5
P. Glaskowsky
2003
Corpus ID: 63640532