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POWER5
Known as:
POWER5+
The POWER5 is a microprocessor developed and fabricated by IBM. It is an improved version of the POWER4. The principal improvements are support for…
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2012
2012
Test Generation Approach for Post-Silicon Validation of High End Microprocessor
S. Sadasivam
,
Sangram Alapati
,
Varun Mallikarjunan
15th Euromicro Conference on Digital System…
2012
Corpus ID: 9857138
Post-Silicon Validation faces numerous challenges in the areas of test generation efficiency, time utilization and comprehensive…
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2011
2011
Pacific symposium on biocomputing 2011
G. Bebek
,
M. Chance
,
+20 authors
M. Ramoni
2011
Corpus ID: 90130813
The sixth Pacific Symposium on Biocomputing (PSB) marks the first PSB held after the completion of the "rough draft" of the Human…
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2011
2011
Performance modeling of hybrid MPI/OpenMP scientific applications on large-scale multicore supercomputers
Xingfu Wu
,
V. Taylor
Journal of computer and system sciences (Print)
2011
Corpus ID: 12621248
2009
2009
Scalable RDMA performance in PGAS languages
Montse Farreras
,
G. Almási
,
Calin Cascaval
,
Toni Cortes
IEEE International Symposium on Parallel…
2009
Corpus ID: 17458580
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor…
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2008
2008
Software-Controlled Priority Characterization of POWER5 Processor
C. Boneti
,
F. Cazorla
,
R. Gioiosa
,
A. Buyuktosunoglu
,
Chen-Yong Cher
,
M. Valero
International Symposium on Computer Architecture
2008
Corpus ID: 13926925
Due to the limitations of instruction-level parallelism, thread-level parallelism has become a popular way to improve processor…
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Highly Cited
2007
Highly Cited
2007
Multicore Surprises: Lessons Learned from Optimizing Sweep3D on the Cell Broadband Engine
F. Petrini
,
G. Fossum
,
Juan Fernández
,
A. Varbanescu
,
M. Kistler
,
M. Perrone
IEEE International Parallel and Distributed…
2007
Corpus ID: 14291953
The Cell Broadband Engine (BE) processor provides the potential to achieve an impressive level of performance for scientific…
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2006
2006
Integrating Multiple Forms of Multithreaded Execution on SMT Processors: A Quantitative Study with Scientific Workloads
Wang M.
,
Matthew Curtis-Maury
,
Ta-Yang Wang
,
C. Antonopoulos
,
Dimitrios S. Nikolopoulos
2006
Corpus ID: 14943816
Most scientific applications have high degrees of parallelism and thread-level parallel execution appears to be a natural choice…
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2004
2004
Timing uncertainty measurements on the Power5 microprocessor
P. Restle
,
Robert L. Franch
,
+5 authors
J. Clabes
IEEE International Solid-State Circuits…
2004
Corpus ID: 39059879
On-chip timing measurement (Skitter) circuits are included on the Power5 microprocessor. By cross-coupling the 3 Skitter…
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Highly Cited
2004
Highly Cited
2004
Design and Implementation of the POWER5 TM Microprocessor
J. Clabes
,
J. Friedrich
,
+16 authors
S. Dodson
2004
Corpus ID: 18049040
offers significantly increased performance over previous POWER designs by incorporating simultaneous multithreading, an enhanced…
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2004
2004
Design and implementation of the POWER5/spl trade/ microprocessor
J. Clabes
,
J. Friedrich
,
+18 authors
S. Dodson
International Conference on Integrated Circuit…
2004
Corpus ID: 10089151
POWER5/sup TM/ is the next generation of IBM's POWER microprocessors. This design, sets a new standard of server performance by…
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