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PCI Express
Known as:
PCIe 1.0
, PCIe 2.0
, PCIe 1.1
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PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed serial computer expansion bus standard…
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Related topics
Related topics
50 relations
AMD 580 chipset series
Accelerated Graphics Port
Advanced Graphics Riser
Backward compatibility
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
An Empirical Study of Intel Xeon Phi
Jianbin Fang
,
A. Varbanescu
,
H. Sips
,
Lilun Zhang
,
Yonggang Che
,
Chuanfu Xu
arXiv.org
2013
Corpus ID: 1066803
With at least 50 cores, Intel Xeon Phi is a true many-core architecture. Featuring fairly powerful cores, two cache levels, and…
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Highly Cited
2012
Highly Cited
2012
The tradeoffs of fused memory hierarchies in heterogeneous computing architectures
Kyle Spafford
,
J. Meredith
,
Seyong Lee
,
Dong Li
,
P. Roth
,
J. Vetter
ACM International Conference on Computing…
2012
Corpus ID: 13219223
With the rise of general purpose computing on graphics processing units (GPGPU), the influence from consumer markets can now be…
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2012
2012
Speedy bus mastering PCI express
Ray Bittner
International Conference on Field-Programmable…
2012
Corpus ID: 6417296
PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in…
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2012
2012
APEnet+: a 3D Torus network optimized for GPU-based HPC Systems
R. Ammendola
,
A. Biagioni
,
+7 authors
P. Vicini
2012
Corpus ID: 62163519
In the supercomputing arena, the strong rise of GPU-accelerated clusters is a matter of fact. Within INFN, we proposed an…
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Highly Cited
2011
Highly Cited
2011
A 40 nm 16-Core 128-Thread SPARC SoC Processor
Jinuk Luke Shin
,
Dawei Huang
,
+9 authors
Allan Strong
IEEE Journal of Solid-State Circuits
2011
Corpus ID: 8727430
This fourth generation UltraSPARC T3 SoC processor implements sixteen 8-threaded SPARC cores to double on-chip thread count and…
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2009
2009
Implementation of a Lattice–Boltzmann method for numerical fluid mechanics using the nVIDIA CUDA technology
E. Riegel
,
T. Indinger
,
N. Adams
Computer Science - Research and Development
2009
Corpus ID: 26091808
AbstractThe Lattice–Boltzmann method (LBM) is a distribution-function based approach to numerical fluid mechanics. Due to the…
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2004
2004
Performance evaluation of InfiniBand with PCI Express
Jiuxing Liu
,
Amith R. Mamidala
,
Abhinav Vishnu
,
D. Panda
Proceedings. 12th Annual IEEE Symposium on High…
2004
Corpus ID: 14381854
We present an initial performance evaluation of InfiniBand HCAs (host channel adapters) from Mellanox with PCI Express interfaces…
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Highly Cited
2003
Highly Cited
2003
PCI Express System Architecture
Ravi Budruk
,
Don Anderson
,
E. Solari
2003
Corpus ID: 109740172
Mindshare and best selling author Ed Solari, join forces to present a book on the newest bus architecture, PCI Express. PCI…
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Highly Cited
2002
Highly Cited
2002
Jitter Testing for Gigabit Serial Communication Transceivers
Y. Cai
,
B. Laquai
,
Kent Luehman
IEEE Design & Test of Computers
2002
Corpus ID: 7837787
Proper testing of transceivers requires the ability not only to measure generated jitter but also to inject in-band as well as…
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2000
2000
Better Adaptive Diagnosis of Hypercubes
E. Kranakis
,
A. Pelc
IEEE Trans. Computers
2000
Corpus ID: 7724355
We consider the problem of adaptive fault diagnosis in hypercube multiprocessor systems. Processors perform tests on one another…
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