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PCI Express
Known as:
PCIe 1.0
, PCIe 2.0
, PCIe 1.1
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PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe, is a high-speed serial computer expansion bus standard…
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Related topics
Related topics
50 relations
AMD 580 chipset series
Accelerated Graphics Port
Advanced Graphics Riser
Backward compatibility
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
GPUdmm: A high-performance and memory-oblivious GPU architecture using dynamic memory management
Youngsok Kim
,
Jaewon Lee
,
Jae-Eon Jo
,
Jangwoo Kim
International Symposium on High-Performance…
2014
Corpus ID: 12577627
GPU programmers suffer from programmer-managed GPU memory because both performance and programmability heavily depend on GPU…
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2013
2013
Porting to the Intel Xeon Phi: Opportunities and Challenges
Carlos Rosales
XML Technologien für das Semantic Web
2013
Corpus ID: 13186999
This work describes the challenges presented by porting code to the Intel Xeon Phi coprocessor, as well as opportunities for…
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2012
2012
Speedy bus mastering PCI express
Ray Bittner
International Conference on Field-Programmable…
2012
Corpus ID: 6417296
PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in…
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2012
2012
APEnet+: a 3D Torus network optimized for GPU-based HPC Systems
R. Ammendola
,
A. Biagioni
,
+7 authors
P. Vicini
2012
Corpus ID: 62163519
In the supercomputing arena, the strong rise of GPU-accelerated clusters is a matter of fact. Within INFN, we proposed an…
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2012
2012
Aho-Corasick String Matching on Shared and Distributed-Memory Parallel Architectures
Antonino Tumeo
,
Oreste Villa
,
D. Chavarría-Miranda
IEEE Transactions on Parallel and Distributed…
2012
Corpus ID: 5751501
String matching requires a combination of (sometimes all) the following characteristics: high and/or predictable performance…
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Highly Cited
2011
Highly Cited
2011
A 40 nm 16-Core 128-Thread SPARC SoC Processor
Jinuk Luke Shin
,
Dawei Huang
,
+9 authors
Allan Strong
IEEE Journal of Solid-State Circuits
2011
Corpus ID: 8727430
This fourth generation UltraSPARC T3 SoC processor implements sixteen 8-threaded SPARC cores to double on-chip thread count and…
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2011
2011
APEnet+: high bandwidth 3D torus direct network for petaflops scale commodity clusters
R. Ammendola
,
A. Biagioni
,
+9 authors
P. Vicini
arXiv.org
2011
Corpus ID: 17574565
We describe herein the APElink+ board, a PCIe interconnect adapter featuring the latest advances in wire speed and interface…
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2004
2004
Performance evaluation of InfiniBand with PCI Express
Jiuxing Liu
,
Amith R. Mamidala
,
Abhinav Vishnu
,
D. Panda
Proceedings. 12th Annual IEEE Symposium on High…
2004
Corpus ID: 14381854
We present an initial performance evaluation of InfiniBand HCAs (host channel adapters) from Mellanox with PCI Express interfaces…
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Highly Cited
2003
Highly Cited
2003
PCI Express System Architecture
Ravi Budruk
,
Don Anderson
,
E. Solari
2003
Corpus ID: 109740172
Mindshare and best selling author Ed Solari, join forces to present a book on the newest bus architecture, PCI Express. PCI…
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Highly Cited
2002
Highly Cited
2002
Jitter Testing for Gigabit Serial Communication Transceivers
Y. Cai
,
B. Laquai
,
Kent Luehman
IEEE Design & Test of Computers
2002
Corpus ID: 7837787
Proper testing of transceivers requires the ability not only to measure generated jitter but also to inject in-band as well as…
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