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OpenSPARC
Known as:
Open Sparc
OpenSPARC is an open-source hardware project started in December 2005. The initial contribution to the project was Sun Microsystems' register…
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Related topics
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17 relations
Field-programmable gate array
History of general-purpose CPUs
LEON
Microprocessor
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding
Xueyan Wang
,
Qiang Zhou
,
Yici Cai
,
G. Qu
Integr.
2019
Corpus ID: 69456925
2016
2016
More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs
Taigon Song
,
Shreepad Panth
,
Yoo-Jin Chae
,
S. Lim
IEEE Transactions on Computer-Aided Design of…
2016
Corpus ID: 15630972
Low-power is one of the key driving forces in modern very large scale integration systems. Recent studies show that 3-D…
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2014
2014
A Coverage Guided Mining Approach for Automatic Generation of Succinct Assertions
David Sheridan
,
Lingyi Liu
,
Hyungsul Kim
,
Shobha Vasudevan
27th International Conference on VLSI Design and…
2014
Corpus ID: 9507968
Machine learning techniques are widely employed for automatic assertion generation in hardware verification. Our previous method…
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2014
2014
Aging-Aware Design of Microprocessor Instruction Pipelines
Fabian Oboril
,
M. Tahoori
IEEE Transactions on Computer-Aided Design of…
2014
Corpus ID: 17492231
As complementary metal-oxide-semiconductor technologies enter nanometer scales, microprocessors become more vulnerable to…
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Highly Cited
2013
Highly Cited
2013
Security analysis of integrated circuit camouflaging
Jeyavijayan Rajendran
,
Michael Sam
,
O. Sinanoglu
,
R. Karri
Conference on Computer and Communications…
2013
Corpus ID: 1550580
Camouflaging is a layout-level technique that hampers an attacker from reverse engineering by introducing, in one embodiment…
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2010
2010
High-Level Design and Validation of the BlueSPARC Multithreaded Processor
Eric S. Chung
,
J. Hoe
IEEE Transactions on Computer-Aided Design of…
2010
Corpus ID: 1378766
This paper presents our experiences in using high-level methods to design and validate a 16-way multithreaded microprocessor…
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Highly Cited
2009
Highly Cited
2009
GCS: High-performance gate-level simulation with GPGPUs
Debapriya Chatterjee
,
A. Deorio
,
V. Bertacco
Design, Automation & Test in Europe Conference…
2009
Corpus ID: 6259151
Highly Cited
2008
Highly Cited
2008
CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns
Yanjing Li
,
S. Makar
,
S. Mitra
Design, Automation and Test in Europe
2008
Corpus ID: 8372009
CASP, concurrent autonomous chip self-test using stored test patterns, is a special kind of self-test where a system tests itself…
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Review
2008
Review
2008
OpenSPARC - A Scalable Chip Multi-Threading Design
Dwayne Lee
International Conference on VLSI Design
2008
Corpus ID: 43617682
Summary form only given. This tutorial is about OpenSPARC and provides details on the first chip multi-threading 64-bit, 32…
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2008
2008
Fault Tolerance in OpenSPARC Multicore Architecture Using Core Virtualization
K. Chandrasekar
,
Revathi Ananthachari
,
S. Seshadri
,
R. Parthasarathi
2008
Corpus ID: 18791407
In multicore architecture, fault tolerance issues will increase with increase in number of cores. Size scaling has been…
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