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OpenRISC

Known as: Or1k 
OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing (RISC… Expand
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ARM architectureApplication-specific integrated circuitC++Comparison of instruction set architectures
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
The Secret Processor Will Go to the Ball: Benchmark Insider-Proof Encrypted Computing
‘Encrypted computing’ is an approach to preventing insider attacks by the privileged operator against the unprivileged user on a… Expand
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2018
2018
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving
This paper proposes a mean time-to-failure (MTTF) aware design methodology for minimizing power dissipation while satisfying… Expand
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2016
2016
Implementation of an OpenRISC based SoC and Linux Kernel installation on FPGA
Embedded system designs and applications have been more common today. The aim of this study is to tell how to implement open… Expand
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2015
2015
PULP: A parallel ultra low power platform for next generation IoT applications
 
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2015
2015
Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation
Specialization and accelerators are being proposed as an effective way to address the slowdown of Dennard scaling. DySER is one… Expand
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2013
2013
Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration
Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed to solve the… Expand
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2011
2011
Constant-bandwidth supply for priority processing
Today's consumer electronic devices feature multiple applications which have to share scarcely available resources. We consider a… Expand
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2010
2010
Active Fault-Tolerance Low Power Multiplier with OpenRISC Platform
Today's embedded systems are commonly required to be light, small, and power-efficient. However, applications for embedded… Expand
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2008
2008
Design and implementation of a debugging system for OpenRISC processor
A gdb-based debugging system for OpenRISC1200 Processor based on IEEE1149.1 JTAG interface is developed. Unlike usual gdb-based… Expand
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2006
2006
Floorplan and power/ground network co-synthesis for fast design convergence
As technology advances, the metal width decreases while the global wire length increases. This trend makes the resistance of the… Expand
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