OpenRISC

Known as: Or1k 
OpenRISC is a project to develop a series of open source instruction set architectures based on established reduced instruction set computing (RISC… Expand
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ARM architectureApplication-specific integrated circuitC++Comparison of instruction set architectures
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Papers overview

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2016
2016
SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC
Buffer overflow and stack smashing have been one of the most popular software based vulnerabilities in literature. There have… Expand
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2015
2015
Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores
Baseline RISC instruction sets for ultra-low power processors are constantly being tuned to reduce cycle count when executing… Expand
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2014
2014
OpenRISC-based System-on-Chip for digital signal processing
This paper presents the design and implementation of an OpenRISC-based System-on-Chip (SoC), which is composed of hardware cores… Expand
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2013
2013
Shifting Primes on OpenRISC Processors with Hardware Multiplier
Shifting primes have proved its efficiency in CPUs without hardware multiplier such as the located at the MSP430 from Texas… Expand
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2013
2013
Multiplication and Squaring with Shifting Primes on OpenRISC Processors with Hardware Multiplier
Cryptographic primitives are the key component in the security protocols to support the authentication, key management and secure… Expand
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2012
2012
Embedded system with Linux Kernel based on OpenRISC 1200-V3
Embedded system intends to realize portable systems, while reducing chip connect, device size and power dissipation. These… Expand
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2011
2011
A New Solution to GNSS Receiver Baseband Signal Processing SOC Platform Based on OpenRISC Processor
A new solution to GNSS receiver baseband signal processing SoC platform based on OpenRISC CPU is presented. The system hardware… Expand
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2009
2009
Design and Implementation of Performance Counters in an OpenRISC Processor
Performance counters inside the processor can be used to report real-time values of processor performance metrics through… Expand
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2008
2008
Design and implementation of a debugging system for OpenRISC processor
A gdb-based debugging system for OpenRISC1200 Processor based on IEEE1149.1 JTAG interface is developed. Unlike usual gdb-based… Expand
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2006
2006
Implementation of CRC32 Parallel Computing in OpenRISC
The increasing processing speed of RISC CPU/DSP makes it possible to use the microcode program to adapt and process the protocol… Expand
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