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Multiply–accumulate operation

Known as: Fused Multiply Add, MAC-unit, Multiply add 
In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and… 
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Related topics

Related topics

43 relations
ARM Cortex-A5ARM Cortex-MARM architectureAccumulator (computing)

Broader (1)

Digital signal processing

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2006
Highly Cited
2006
A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor
The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single… 
2005
2005
A highly reconfigurable computing array: DSP plane of a 3D heterogeneous SoC
A 3D heterogeneous system on a chip using a stack of planes has recently been proposed. While the sensors are located on the top… 
Highly Cited
2002
Highly Cited
2002
A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias (ASB) architecture
The power dissipation of a digital circuit is minimized by simultaneous control of power supply voltage and body bias. The… 
2001
2001
1 GHz HAL SPARC64/sup R/ Dual Floating Point Unit with RAS features
An IEEE compliant, 1 GHz Sparc64-V Floating-Point Unit (FPU) with reliability-accessibility-serviceability (RAS) features and… 
Highly Cited
2000
Highly Cited
2000
Low power/energy BIST scheme for datapaths
Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these… 
1996
1996
A dual floating point coprocessor with an FMAC architecture
The CPU chip is implemented in a 5-layer metal 0.5 /spl mu/m CMOS process and delivers >360 SPECint92 and >550 SPECfp92. It is an… 
Review
1990
Review
1990
The IBM RISC System/6000 Processor: Hardware Overview
A highly concurrent superscalar second-generation family of RISC workstations and servers is described. The RISC System/6000… 
Highly Cited
1987
Highly Cited
1987
Parallel bit-level pipelined VLSI designs for high-speed signal processing
This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in… 
Highly Cited
1986
Highly Cited
1986
Efficient procedures for finding the optimum innovation in stochastic coders
  • I. TrancosoB. Atal
  • ICASSP '86. IEEE International Conference on…
  • 1986
  • Corpus ID: 60965308
Stochastic linear predictive coders have the potential for producing high quality synthetic speech at bit rates as low as 4.8… 
Highly Cited
1984
Highly Cited
1984
A Wideband Sampling Wattmeter1
The design and operation of a wideband sampling wattmeter capable of measuring distorted power signals with fundamental… 
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