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Multiply–accumulate operation

Known as: Fused Multiply Add, MAC-unit, Multiply add 
In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and… 
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Papers overview

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Highly Cited
2006
Highly Cited
2006
The floating-point unit (FPU) in the synergistic processor element (SPE) of a CELL processor is a fully pipelined 4-way single… 
Highly Cited
2002
Highly Cited
2002
The power dissipation of a digital circuit is minimized by simultaneous control of power supply voltage and body bias. The… 
2001
2001
An IEEE compliant, 1 GHz Sparc64-V Floating-Point Unit (FPU) with reliability-accessibility-serviceability (RAS) features and… 
Highly Cited
2000
Highly Cited
2000
Power in processing cores (microprocessors, DSPs) is primarily consumed in the functional modules of the datapath. Among these… 
2000
2000
Sleep-transistors are used to reduce standby power in large modules of integrated circuits [1,4]. With increasing leakage, it is… 
Review
1990
Review
1990
A highly concurrent superscalar second-generation family of RISC workstations and servers is described. The RISC System/6000… 
Highly Cited
1987
Highly Cited
1987
This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in… 
1987
1987
Digital signal processors are defined, and the characteristics that must be considered by the engineer are discussed. The… 
Highly Cited
1986
Highly Cited
1986
  • I. TrancosoB. Atal
  • 1986
  • Corpus ID: 60965308
Stochastic linear predictive coders have the potential for producing high quality synthetic speech at bit rates as low as 4.8… 
Highly Cited
1984
Highly Cited
1984
The design and operation of a wideband sampling wattmeter capable of measuring distorted power signals with fundamental…