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Multiplication algorithm

Known as: Multiplication algorithms, FFT multiplication, Shift and add algorithm 
A multiplication algorithm is an algorithm (or method) to multiply two numbers. Depending on the size of the numbers, different algorithms are in use… 
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ACC0ARM Cortex-MAlgorithmAnalog computer

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
A New Algorithm for Inversion mod pk
A new algorithm for computing x = a − 1 (mod p k ) is introduced. It is based on the exact solution of linear equations using p… 
2017
2017
Implementation of 24 bit high speed floating point vedic multiplier
The computational complexity of various data processing applications is vastly reduced when signals are represented in the… 
2008
2008
A Technique for Accelerating Characteristic 2 Elliptic Curve Cryptography
In this paper we describe a novel approach for speeding up the computations of characteristic 2 elliptic curve cryptography… 
2007
2007
A Highly Parallel FPGA based IEEE-754 Compliant Double-Precision Binary Floating-Point Multiplication Algorithm
There is increasing demand for fast floating-point arithmetic support to make field programmable gate arrays (FPGAs) a practical… 
2003
2003
Low power multiplication algorithm for switching activity reduction through operand decomposition
A novel low power multiplication algorithm for reducing switching activity through operand decomposition is proposed. Our… 
2000
2000
Analytical redundancy based approach for concurrent fault detection in linear digital systems
With the advent of VLSI technology, large numbers of processing elements which cooperate with each other to achieve a complex… 
1998
1998
Hardware for computing modular multiplication algorithm
This paper examines the characteristics of an alternative architecture for computing a modular multiplication based on Montgomery… 
1994
1994
Cellular automata based VLSI architecture for computing multiplication and inverses in GF(2/sup m/)
Finite fields have proved to be very useful in error correcting codes, combinatorial design and many cryptographic applications… 
1985
1985
Design and application of a 2500-gate bipolar macrocell array
A very high-speed 2500-gate Si bipolar macrocell array has been developed using a novel macrocell design approach and a 1-/spl mu… 
1970
1970
High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm
This paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary… 
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