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Multiple encryption
Known as:
Superencryption
, Cascade ciphering
, Cascaded encryption
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Multiple encryption is the process of encrypting an already encrypted message one or more times, either using the same or a different algorithm. It…
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Related topics
Related topics
15 relations
Cipher
Cipher Department of the High Command of the Wehrmacht
Code (cryptography)
Cryptanalysis
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Broader (1)
Cryptography
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Implementation and Control of a Hybrid Multilevel Converter with Floating DC-links for Current Waveform Improvement
Y. Satish
,
P. Kishore
2011
Corpus ID: 14788114
Multilevel converters offer advantages in terms of the output waveform quality due to the increased number of levels used in the…
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Highly Cited
2010
Highly Cited
2010
A hybrid cascaded multilevel inverter application for renewable energy resources including a reconfiguration technique
S. Khomfoi
,
Nattapat Praisuwanna
,
L. Tolbert
IEEE Energy Conversion Congress and Exposition
2010
Corpus ID: 17364587
A hybrid cascaded multilevel inverter application for renewable energy resources including a reconfiguration technique is…
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Highly Cited
2006
Highly Cited
2006
Cascadability and Regenerative Properties of SOA All-Optical DPSK Wavelength Converters
P. Vorreau
,
A. Marculescu
,
+9 authors
J. Leuthold
IEEE Photonics Technology Letters
2006
Corpus ID: 5882934
A novel all-optical differential phase-shift keying wavelength converter based on semiconductor optical amplifier nonlinearities…
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Highly Cited
2005
Highly Cited
2005
A new two-stage sharpened comb decimator
G. Jovanovic-Dolecek
,
S. Mitra
IEEE Transactions on Circuits and Systems Part 1…
2005
Corpus ID: 23553118
This paper presents a new sharpened comb decimator structure consisting of a cascade of a comb-filter based decimator and a…
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Highly Cited
2004
Highly Cited
2004
Nanolab: a tool for evaluating reliability of defect-tolerant nano architectures
D. Bhaduri
,
S. Shukla
IEEE Computer Society Annual Symposium on VLSI
2004
Corpus ID: 12413346
As silicon manufacturing technology reaches the nanoscale, architectural designs need to accommodate the uncertainty inherent at…
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2003
2003
Second-order filter response with series-coupled silica microresonators
A. Savchenkov
,
V. Ilchenko
,
T. Handley
,
L. Maleki
IEEE Photonics Technology Letters
2003
Corpus ID: 2957678
We have demonstrated an approach for fabricating a photonic filter with second-order response function. The filter consists of…
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Highly Cited
1998
Highly Cited
1998
A data-interlacing architecture with two-dimensional data-reuse for full-search block-matching algorithm
Yeong-Kang Lai
,
Liang-Gee Chen
IEEE Trans. Circuits Syst. Video Technol.
1998
Corpus ID: 460468
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search blockmatching…
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Highly Cited
1994
Highly Cited
1994
Neural network-based dynamic channel assignment for cellular mobile communication systems
P.T.H. Chan
,
M. Palaniswami
,
D. Everitt
1994
Corpus ID: 61872184
Conventional dynamic channel assignment schemes are both time-consuming and algorithmically complex. An alternative approach…
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Highly Cited
1993
Highly Cited
1993
FASTUS: A System for Extracting Information from Text
Jerry R. Hobbs
,
D. Appelt
,
J. Bear
,
David J. Israel
,
Megumi Kameyalna
,
M. Tyson
Human Language Technology - The Baltic Perspectiv
1993
Corpus ID: 16255594
FASTUS is a (slightly permuted) acronym for Finite State Automaton Text Understanding System. It is a system for extracting…
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Highly Cited
1989
Highly Cited
1989
Design of parallel hardware neural network systems from custom analog VLSI 'building block' chips
S. Eberhardt
,
T. Duong
,
A. Thakoor
International Joint Conference on Neural…
1989
Corpus ID: 8845998
Hardware to implement feedforward neural networks has been developed for the evaluation of learning algorithms and prototyping of…
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