Memory barrier

Known as: Barrier, Fence instruction, Membar 
A memory barrier, also known as a membar, memory fence or fence instruction, is a type of barrier instruction that causes a central processing unit… (More)
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Topic mentions per year

Topic mentions per year

1995-2018
024619952018

Papers overview

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2013
2013
Chase and Lev's concurrent deque is a key data structure in shared-memory parallel programming and plays an essential role in… (More)
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2013
2013
This paper addresses the problem of verifying and correcting programs when they are moved from a sequential consistency execution… (More)
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2013
2013
We introduce MEMORAX, a tool for the verification of control state reachability (i.e., safety properties) of concurrent programs… (More)
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2012
2012
A concurrent work-stealing algorithm is analysed to discover necessary positions for memory barriers. The analysis is targeted at… (More)
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Highly Cited
2011
Highly Cited
2011
FastFlow is a programming framework specifically targeting cache-coherent shared-memory multicores. It is implemented as a stack… (More)
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2011
2011
This paper addresses the problem of verifying and correcting programs when they are moved from a sequential consistency execution… (More)
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2010
2010
XSTM is a software transactional memory that can be extended by pluggable components. Extensions can access transactions read and… (More)
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2009
2009
So what possessed CPU designers to cause them to inflict memory barriers on poor unsuspecting SMP software designers? In short… (More)
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2009
2009
Shared-memory multi-core architectures are becoming increasingly popular. While their parallelism and peak performance is ever… (More)
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Highly Cited
2003
Highly Cited
2003
In general, the hardware memory consistency model in a multiprocessor system is not identical to the memory model at the… (More)
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