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Manhattan wiring
Known as:
Right-angle wiring
, Right angle wiring
, Manhattan (disambiguation)
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Manhattan wiring (also known as right-angle wiring) is a technique for laying out circuits in computer engineering. Inputs to a circuit (specifically…
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Related topics
Related topics
3 relations
Computer engineering
Programmable logic array
Taxicab geometry
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
RWCap: A Floating Random Walk Solver for 3-D Capacitance Extraction of Very-Large-Scale Integration Interconnects
Wenjian Yu
,
Hao Zhuang
,
Chao Zhang
,
Gang Hu
,
Zhi Liu
IEEE Transactions on Computer-Aided Design of…
2013
Corpus ID: 16351864
A floating random walk (FRW) solver, called RWCap, is presented for the capacitance extraction of very-large-scale integration…
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2008
2008
CLCP – A Distributed Cross-Layer Commit Protocol for Mobile Ad Hoc Networks
S. Obermeier
,
S. Böttcher
,
Dominik Kleine
IEEE International Symposium on Parallel and…
2008
Corpus ID: 7219951
Transaction processing in mobile ad hoc networks must take network problems like node disconnection, message loss, and network…
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2000
2000
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching
Qiao Li
,
S. Kang
ACM Great Lakes Symposium on VLSI
2000
Corpus ID: 1952033
In non-Manhattan geometry layout extraction, polygon to trapezoid decomposition is an indispensable step. Its efficiency and the…
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1999
1999
A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits
W. Pleskacz
,
C. Ouyang
,
Wojciech Maly
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1999
Corpus ID: 15826604
This paper describes an algorithm for the extraction of the critical area for opens. The presented algorithm allows for the…
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1991
1991
Novel routing schemes for IC layout part I: two-layer channel routing
Deborah C. Wang
28th ACM/IEEE Design Automation Conference
1991
Corpus ID: 6039586
We present new channel routing algorithms and theory that consider the characteristic of net crossings. ‘llte routing strategy is…
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1991
1991
Parallel algorithms for VLSI circuit extraction
K. Belkhale
,
P. Banerjee
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1991
Corpus ID: 1306776
The authors propose parallel algorithms to speedup the VLSI circuit extraction task. Given a VLSI layout as input, the problem of…
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1987
1987
A Formal Approach to Design-Rule Checking
H. Modarres
,
R. Lomax
IEEE Transactions on Computer-Aided Design of…
1987
Corpus ID: 33958738
This paper describes the development of a layout model and the theoretical basis for a relatively technology-independent, false…
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1987
1987
KAHLUA: A Hierarchical Circuit Disassembler
Bill Lin
,
A. Newton
24th ACM/IEEE Design Automation Conference
1987
Corpus ID: 1391493
A new tool called a circuit disassembler has been developed to transform a mask level layout into an equivalent symbolic layout…
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Highly Cited
1986
Highly Cited
1986
Efficient Algorithms for Geometric Graph Search Problems
H. Imai
,
Takao Asano
SIAM journal on computing (Print)
1986
Corpus ID: 1754571
In this paper, we show that many graph search problems can be solved quite efficiently for a geometric intersection graph of…
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1986
1986
An integer based hierarchical representation for VLSI
T. Whitney
,
C. Mead
1986
Corpus ID: 36146837
Geometries with 45° line segments are often used in integrated circuit layouts, since they can save considerable area. In the…
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