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Inverter (logic gate)
Known as:
4049
, Hex Inverter
, NO gate
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In digital logic, an inverter or NOT gate is a logic gate which implements logical negation. The truth table is shown on the right.
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Related topics
Related topics
38 relations
7400 series
AND gate
And-inverter graph
Boolean algebra
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2013
Highly Cited
2013
Synthesis Design of Dual-Band Bandpass Filters With $\lambda/4$ Stepped-Impedance Resonators
Songbai Zhang
,
Lei Zhu
IEEE transactions on microwave theory and…
2013
Corpus ID: 14466424
<?Pub Dtl?>This paper proposes a class of dual-band bandpass filters with <formula formulatype="inline"><tex Notation="TeX…
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Highly Cited
2009
Highly Cited
2009
Extended-Boost <formula formulatype="inline"><tex Notation="TeX">$Z$</tex></formula>-Source Inverters
C. Gajanayake
,
LuoFang Lin
,
Gooi Hoay Beng
,
So Ping Lam
,
Siow Lip Kian
IEEE transactions on power electronics
2009
Corpus ID: 19523371
The Z-source inverter has gained popularity as a single-stage buck-boost inverter topology among many researchers. However, its…
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Highly Cited
2007
Highly Cited
2007
Eliminating ground current in a transformerless photovoltaic application
Óscar López Sánchez
,
Remus Teodorescu
,
F. Freijedo
,
J. Doval‐Gandoy
IEEE Power Engineering Society General Meeting
2007
Corpus ID: 47555240
A single phase converter can be used for low-power grid connected applications. In photovoltaic applications it is possible to…
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Highly Cited
2005
Highly Cited
2005
Direct model predictive control - a new direct predictive control strategy for electrical drives
A. Linder
,
R. Kennel
EPE
2005
Corpus ID: 14664766
Since more than 20 years the so-called "field oriented control" is state-of-the-art for electrical drives. Strategies based on…
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Highly Cited
2003
Highly Cited
2003
A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation
M. Mansuri
,
C. Yang
IEEE J. Solid State Circuits
2003
Corpus ID: 15061037
This paper describes a fully integrated low-jitter CMOS phase-locked loop and clock buffer for low-power digital systems with a…
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Highly Cited
2002
Highly Cited
2002
A 31-level cascade inverter for power applications
C. Lee
,
R. Hui
,
H. Chung
IEEE transactions on industrial electronics…
2002
Corpus ID: 43489296
Power inverter modules fed with separate DC voltage sources of voltage ratio 1:2:4:8 are connected to form a cascade multilevel…
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Review
1999
Review
1999
Opportunities for harmonic cancellation with carrier based PWM for two-level and multi-level cascaded inverters
D. G. Holmes
,
B. McGrath
Conference Record of the IEEE Industry…
1999
Corpus ID: 88495749
PWM strategies have been the subject of many years of research effort, and the merits of the various alternatives investigated…
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Highly Cited
1988
Highly Cited
1988
Performance characterization of a new discrete pulse modulated current regulator
T. Habetler
,
D. Divan
Conference Record of the IEEE Industry…
1988
Corpus ID: 17138209
A discrete pulse-modulated current regulator which controls a space (d-q) vector that describes the load current is introduced…
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Highly Cited
1987
Highly Cited
1987
An SOI voltage-controlled bipolar-MOS device
J. Colinge
IEEE Transactions on Electron Devices
1987
Corpus ID: 27821772
This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI…
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Highly Cited
1982
Highly Cited
1982
Computer-Aided Design of PWM Inverter Systems
S. R. Bowes
,
R. R. Clements
1982
Corpus ID: 60646262
The increasing availability of digital computers now makes the computer-aided design of powerelectronic systems an attractive and…
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