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Front-end processor
Known as:
Communications controller
, Processor
, Front end processor
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A front end processor (FEP), or a communications processor, is a small-sized computer which interfaces to the host computer a number of networks…
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Related topics
Related topics
15 relations
CP-6
Computer
Computer terminal
Control unit
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
UVM based approaches to functional verification of communication controllers of microprocessor systems
I. Stotland
,
D. Shpagilev
,
N. Starikovskaya
East-West Design & Test Symposium
2016
Corpus ID: 22011106
The approach to functional verification of communication controllers based on developing layered UVM test systems is considered…
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2015
2015
LS2085/8A Freescale's new QorlQ Layerscape communications processor
Zhengqi Xu
IEEE Hot Chips Symposium
2015
Corpus ID: 26240714
Review
2014
Review
2014
Stereo Vision Algorithms Suited to Constrained FPGA Cameras
Stefano Mattoccia
2014
Corpus ID: 60297925
The advent of cheap RGBD active 3D sensors, such as those based on structured light (e.g., the Microsoft Kinect) or those based…
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2014
2014
MODELING OF LOW POWER SERIAL INTERFACE TO HIGH SPEED ETHERNET ON FPGA
Padmaneela Nallani
,
T. V. Reddy
2014
Corpus ID: 55443965
The FPGA-based GIGABIT Ethernet MAC controller and universal asynchronous serial communication controller are designed and…
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2008
2008
THE SPECIFICATION AND IMPLEMENTATION OF A MODEL OF COMPUTATION
R. Thibodeaux
2008
Corpus ID: 53382812
2008
2008
Differentially Encoded LDPC Codes—Part II: General Case and Code Optimization
Jing Li
EURASIP Journal on Wireless Communications and…
2008
Corpus ID: 7334098
This two-part series of papers studies the theory and practice of differentially encoded low-density parity-check (DE-LDPC) codes…
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2007
2007
STATUS OF THE DIAMOND FAST ORBIT FEEDBACK SYSTEM
M. Abbott
,
J. Dobbing
,
+4 authors
J.Rowl
2007
Corpus ID: 63397185
We present the development of transverse orbit stability control at Diamond. We discuss the low latency feedback loop required to…
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2006
2006
Software implementation of a time-triggered ethernet controller
P. Grillinger
,
A. Ademaj
,
K. Steinhammer
,
H. Kopetz
IEEE International Workshop on Factory…
2006
Corpus ID: 24584142
In this paper we present the architecture of a software implementation of a Time-Triggered Ethernet (TTE) controller. The…
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2002
2002
Slightly-off-specification failures in the time-triggered architecture
A. Ademaj
Seventh IEEE International High-Level Design…
2002
Corpus ID: 35774176
Slightly-off-specification (SOS) failures can occur at the interface between the analog and the digital world. If an erroneous…
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2002
2002
Communication synthesis techniques for multiprocessor systems
A. Zitouni
,
M. Abid
,
K. Torki
,
R. Tourki
2002
Corpus ID: 57118446
This paper presents an interactive communication synthesis approach for multiprocessor systems. The aim of the approach consists…
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