Skip to search formSkip to main contentSkip to account menu

EEMBC

Known as: Embedded Microprocessor Benchmark Consortium 
EEMBC, the Embedded Microprocessor Benchmark Consortium, is a non-profit organization formed in 1997 with the aim of developing performance… 
Wikipedia (opens in a new tab)

Related topics

Related topics

21 relations
AVR32AndroidBenchmark (computing)C standard library

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
The Case for Flexible ISAs: Unleashing Hardware and Software
For a long time the Instruction Set Architecture (ISA) has been the firm contract between software and hardware. This firm… 
2016
2016
Ultralow-Power Designs
2012
2012
Timed model checking with abstractions: towards worst-case response time analysis in resource-sharing manycore systems
Multicore architectures are increasingly used nowadays in embedded real-time systems. Parallel execution of tasks feigns the… 
2010
2010
Support of cross calls between a microprocessor and FPGA in CPU-FPGA coupling architecture
The coupling architecture containing an FPGA device and a microprocessor has been widely used to accelerate microprocessor… 
2009
2009
Customized kernel execution on reconfigurable hardware for embedded applications
2008
2008
Optimal Huffman Tree-Height Reduction for Instruction-Level Parallelism
Exposing and exploiting instruction-level parallelism (ILP) is a key component of high performance for modern processors. For… 
2007
2007
Towards an energy efficient branch prediction scheme using profiling, adaptive bias measurement and delay region scheduling
Dynamic branch predictors account for between 10% and 40% of a processor's dynamic power consumption. This power cost is… 
2007
2007
Increasing data-bandwidth to instruction-set extensions through register clustering
The conflicting requirements of performance and flexibility in today 's embedded system market are forcing system designers to… 
2005
2005
Implementing low-power configurable processors - practical options and tradeoffs
  • J. WeiC. Rowen
  • Proceedings - Design Automation Conference
  • 2005
  • Corpus ID: 15045189
Configurable processors enable dramatic gains in energy efficiency, relative to traditional fixed instruction-set processors… 
2004
2004
Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units
Instruction Level Parallelism (ILP) machines, such as Very Long Instruction Word (VLIW) architectures, and customised… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)