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Distributed Concurrent Versions System
Known as:
DCVS
The Distributed Concurrent Versions System (DCVS) is a distributed revision control system that enables software developers working on locally…
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Concurrent Versions System
Distributed version control
List of version control software
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
A frame-level encoder rate control scheme for transform domain Wyner-Ziv video coding
Jian Chen
,
Shuai Zheng
,
Qing Hu
,
Yonghong Kuo
Multimedia tools and applications
2017
Corpus ID: 1029538
Available distributed video coding codecs are mostly based on decoder rate control scheme where the parity bits for decoding can…
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2011
2011
Performance analysis of video encoders for wireless video sensor networks
N. Imran
,
Boon-Chong Seet
,
A. Fong
Proceedings of IEEE Pacific Rim Conference on…
2011
Corpus ID: 14437318
Wireless video sensor networks (WVSNs) have drawn significant attention in recent years due to the advent of low-cost…
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2006
2006
A Novel DCVS Tree Reduction Algorithm
O. Kavehie
,
K. Navi
,
T. Nikoubin
,
M. Rouholamini
IEEE International Conference on IC Design and…
2006
Corpus ID: 36124385
This paper presents a new method to simplify the implemented functions by differential cascode voltage switch (DCVS) tree using a…
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2006
2006
Fault-Tolerance of Robust Feed-Forward Architecture Using Single-Ended and Differential Deep-Submicron Circuits Under Massive Defect Density
M. Stanisavljevic
,
A. Schmid
,
Y. Leblebici
The IEEE International Joint Conference on…
2006
Corpus ID: 473066
An assessment of the fault-tolerance properties of single-ended and differential signaling is shown in the context of a high…
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2005
2005
A voltage level converter circuit design with low power consumption
Chin Ping-Yuan
,
Yu Chien-Cheng
International Conference on ASIC
2005
Corpus ID: 15223287
A conventional level converter, named the dual cascode voltage switch (DCVS), interposed between gates operating on different…
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2004
2004
Enhanced 32-bit carry look-ahead adder using multiple output enable-disable CMOS differential logic
Mário C. B. Osorio
,
Carlos A. Sampaio
,
A. Reis
,
R. Ribas
Proceedings. SBCCI . 17th Symposium on Integrated…
2004
Corpus ID: 13972675
This paper presents an enhanced 32-bit carry look-ahead (CLA) adder implemented using the multi-output enable/disable CMOS…
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1997
1997
A true single-phase clocking scheme for low-power and high-speed VLSI
B. Kong
,
Young-Hyun Jun
,
K. Lee
Proceedings of IEEE International Symposium on…
1997
Corpus ID: 61864880
This paper describes a true-single-phase clocking scheme with charge-recycling differential logic (CRDL). The original CRDL…
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1994
1994
The design of fast asynchronous adder structures and their implementation using DCVS logic
M. Renaudin
,
B. El-Hassan
International Symposium on Circuits and Systems
1994
Corpus ID: 10598356
New asynchronous adder structures with high performances and low cost have been designed. Previous work has only reported the…
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1993
1993
Distributed Concurrent Version System
Curtis Olson
1993
Corpus ID: 17942104
This paper describes an extension to the Concurrent Version System (CVS), which facilitates the use of CVS by a group of users in…
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1990
1990
Easily testable DCVS multiplier
A. Takach
,
N. K. Jha
IEEE International Symposium on Circuits and…
1990
Corpus ID: 61242561
Clocked differential cascode voltage switch (DCVS) circuits are dynamic CMOS circuits which have the advantage of being protected…
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