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Review

2014

Review

2014

We present the algorithm and architecture of a BCD parallel multiplier that exploits some properties of two different redundant…

2011

2011

This paper describes the FPGA implementation of a Decimal Floating Point (DFP) adder/subtractor. The design performs addition and…

2010

2010

The paper presents an efficient algorithm to compute base-10 logarithm of a decimal number. The algorithm uses a 64-bit floating…

2010

2010

Decimal floating-point addition is important for financial and business applications. There has been a growing interest in…

2010

2010

This paper presents the first hardware implementation of a fully parallel decimal floating-point fused-multiply-add unit…

2009

2009

This paper describes the design and implementation of a hardware module to calculate the decimal floating-point DFP…

2009

2009

The IEEE Standards Committee recently approved the IEEE 754–2008 Standard for Floating-point Arithmetic, which includes…

2009

2009

This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) logarithmic converter based on the…

2009

2009

We describe the design and implementation of a comprehensive library of transcendental functions for the new IEEE decimal…

2008

2008

Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation…