Skip to search formSkip to main contentSkip to account menu

DPLL algorithm

Known as: Davis-Putnam-Logemann-Loveland algorithm, Davis–Putnam–Logemann–Loveland algorithm, DPLL-Algorithm 
In computer science, the Davis–Putnam–Logemann–Loveland (DPLL) algorithm is a complete, backtracking-based search algorithm for deciding the… 
Wikipedia (opens in a new tab)

Related topics

Related topics

34 relations
Answer set programmingAutomated planning and schedulingAutomated theorem provingBackjumping

Broader (1)

Constraint programming

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2012
Highly Cited
2012
A 0.004mm2 250μW ΔΣ TDC with time-difference accumulator and a 0.012mm2 2.5mW bang-bang digital PLL using PRNG for low-power SoC applications
As digital CMOS technology scales to 32nm and below, small and low-voltage clock and timing generators are in high demand to… 
2007
2007
Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs
Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS… 
2007
2007
Visualizing SAT Instances and Runs of the DPLL Algorithm
SAT-solvers have turned into essential tools in many areas of applied logic like, for example, hardware verification or… 
2005
2005
The Model Evolution Calculus with Equality
In many theorem proving applications, a proper treatment of equational theories or equality is mandatory. In this paper we show… 
Highly Cited
2001
Highly Cited
2001
Backjumping for Quantified Boolean Logic satisfiability
1996
1996
Frequency granularity in digital phaselock loops
The frequency of a digital phaselock loop (DPLL) is necessarily quantized. Feedback around the quantizing nonlinearity leads to a… 
Highly Cited
1996
Highly Cited
1996
A stereo multi-bit /spl Sigma//spl Delta/ D/A with asynchronous master-clock interface
An oversampling DAC that generates low-jitter, synchronous and oversampled clock internally uses an on-chip digital phase-locked… 
Highly Cited
1990
Highly Cited
1990
A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS
A high-speed hybrid clock recovery circuit composed of an analog phase-locked loop (PLL) and a digital PLL (DPLL) for disk drive… 
Highly Cited
1989
Highly Cited
1989
All digital phase-locked loop: concepts, design and applications
The concepts of an all digital phase-locked loop (DPLL), which contains a purely digital phase detector, loop filter and voltage… 
Highly Cited
1989
Highly Cited
1989
Secure random number generation using chaotic circuits
The authors show how to use a chaotic circuit as a secure random number generator and given an example using a first-order… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)