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Coremark
CoreMark is a benchmark that aims to measure the performance of central processing units (CPU) used in embedded systems. It was developed in 2009 by…
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Benchmark (computing)
Central processing unit
Cyclic redundancy check
Dhrystone
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
An Adaptive Multitasking Superscalar Processor
Mong Tee Sim
,
Qing Yi
International Conference on Innovative Computing…
2019
Corpus ID: 215799656
For CPUs, the design tradeoffs between high-performance computing and low-power consumption can be made a run-time decision…
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2018
2018
Reduction of Instruction Increase Overhead by STRAIGHT Compiler
Toru Koizumi
,
Satoshi Nakae
,
A. Fukuda
,
H. Irie
,
S. Sakai
Sixth International Symposium on Computing and…
2018
Corpus ID: 57191747
It is effective to remove false dependencies to efficiently perform out-of-order (OoO) execution which improves single thread…
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2018
2018
Energy-Delay Trade-Offs in Instruction Register File Design
Joonas Multanen
,
Heikki O. Kultala
,
P. Jääskeläinen
IEEE Nordic Circuits and Systems Conference…
2018
Corpus ID: 56178684
In order to decrease latency and energy consumption, processors use hierarchical memory systems to store temporally and spatially…
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2017
2017
A Case Study of Energy Efficiency on a Heterogeneous Multi-Processor
Hitoshi Oi
Sigmetrics Performance Evaluation Review
2017
Corpus ID: 21407703
In this extended abstract, we present a case study of powerefficiency on a heterogeneous multi-core processor, Exynos 5422 based…
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2017
2017
TLM Virtual Platform for Fast and Accurate Power Estimation
A. Abdel-Haleem
,
M. El-Moursy
International Workshop on Microprocessor Test and…
2017
Corpus ID: 49540883
Power estimation at system-level is essential to address today's growing electronic design challenges with the paradigm shift in…
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2016
2016
The HF-RISC processor: Performance assessment
S. J. Filho
,
Matheus T. Moreira
,
Ney Laert Vilar Calazans
,
Fabiano Hessel
IEEE 7th Latin American Symposium on Circuits…
2016
Corpus ID: 11813797
This paper presents HF-RISC, a 32-bit RISC processor, along with its associated programming toolchain. The instruction set…
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2015
2015
Implementation of the ADELITE Microcontroller for Biomedical Applications
Krzysztof Marcinek
,
Maciej Plasota
,
A. Wielgus
,
W. Pleskacz
IEEE 18th International Symposium on Design and…
2015
Corpus ID: 23391935
Recently, we are witnessing a rapid development in many fields of science, including medicine and healthcare. One of the visible…
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2015
2015
A dual-issue embedded processor for low power devices
Hanni B. Lozano
,
M. Ito
International Conference on Industrial Networks…
2015
Corpus ID: 15843313
While energy efficiency is essential to extend the battery life of embedded devices, performance cannot be ignored. High…
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2015
2015
4.4 Energy-efficient microserver based on a 12-core 1.8GHz 188K-CoreMark 28nm bulk CMOS 64b SoC for big-data applications with 159GB/S/L memory bandwidth system density
R. Luijten
,
Dae Pham
,
R. Clauberg
,
Matteo Cossale
,
H. Nguyen
,
Mihir Pandya
IEEE International Solid-State Circuits…
2015
Corpus ID: 24606866
MicroServers integrate an entire server motherboard into a single Server-on-a-Chip (SoC), excluding DRAM, NOR-boot and power…
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2010
2010
Adapting an FPGA-optimized microprocessor to the MIPS32 instruction set
O. Andersson
,
Karl Bengtsson
2010
Corpus ID: 60992343
Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part…
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