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Coremark
CoreMark is a benchmark that aims to measure the performance of central processing units (CPU) used in embedded systems. It was developed in 2009 by…
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Related topics
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9 relations
Benchmark (computing)
Central processing unit
Cyclic redundancy check
Dhrystone
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Do Your Cores Play Nicely? A Portable Framework for Multi-core Interference Tuning and Analysis
D. Iorga
,
Tyler Sorensen
,
Alastair F. Donaldson
arXiv.org
2018
Corpus ID: 52281829
Multi-core architectures can be leveraged to allow independent processes to run in parallel. However, due to resources shared…
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2015
2015
ParaNut-An Open , Scalable , and Highly Parallel Processor Architecture for FPGA-based Systems
G. Kiefer
,
Mitchell A. Seider
,
M. Schaeferling
2015
Corpus ID: 40447390
The paper presents the ParaNut architecture, a new open and highly scalable processor architecture for FPGAbased systems. The…
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2012
2012
PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP
M. R
,
P. V.
Soft Computing Models in Industrial and…
2012
Corpus ID: 16277749
In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at…
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2011
2011
Explorer Cycle-Accurate Performance Modelling in an Ultra-Fast Just-InTime Dynamic Binary Translation Instruction Set Simulator
Igor Böhm
,
Björn Franke
,
N. Topham
2011
Corpus ID: 67754144
Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and…
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2010
2010
Adapting an FPGA-optimized microprocessor to the MIPS32 instruction set
O. Andersson
,
Karl Bengtsson
2010
Corpus ID: 60992343
Nowadays, FPGAs are large enough to host entire system-on-chip designs, wherein a soft core processor is often an integral part…
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2010
2010
New Block End of Epoch Call Translated Block Function Add Block to Worklist Interpretive Block Simulation Increment Block Simulation Counter Translate Blocks in Worklist Update
Igor Böhm
,
Björn Franke
,
N. Topham
2010
Corpus ID: 67799002
Instruction set simulators (ISS) are vital tools for compiler and processor architecture design space exploration and…
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