Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 222,828,418 papers from all fields of science
Search
Sign In
Create Free Account
Carry flag
Known as:
Carry
, Carry bit
In computer processors the carry flag (usually indicated as the C flag) is a single bit in a system status (flag) register used to indicate when an…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
37 relations
8-bit
ARM architecture
Adjust flag
Arbitrary-precision arithmetic
Expand
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
High Speed Error Tolerant Adder for Multimedia Applications
S. Geetha
,
P. Amritvalli
Journal of electronic testing
2017
Corpus ID: 36190358
In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by…
Expand
2015
2015
High performance 8 bit cascaded carry look ahead adder with precise power consumption
R. Johri
,
S. Akashe
,
Sanjay Sharma
International Journal of Communication Systems
2015
Corpus ID: 205739947
Multiple bit adders like ripple carry adder make the propagation of carry bit very slow and this is the reason why it must be…
Expand
2014
2014
EFFECT OF THE USE OF CRUMB RUBBER IN CONVENTIONAL BITUMEN ON THE MARSHALL STABILITY VALUE
H. Raol
,
A. Parmar
,
D. Patel
,
Jitendra Jayswal
2014
Corpus ID: 136512680
In today’s era, solid waste management is the thrus t area. Out of this various waste materials, plasti c waste, tyre waste and…
Expand
2011
2011
Modeling multi-output filtering effects in PCMOS
Anshul Singh
,
A. Basu
,
K. Ling
,
V. Mooney
Proceedings of International Symposium on VLSI…
2011
Corpus ID: 1950104
A methodology has been proposed recently to predict error rates of cascade structures of blocks in Probabilistic CMOS (PCMOS). It…
Expand
2010
2010
Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains
Thomas B. Preußer
,
R. Spallek
International Conference on Field-Programmable…
2010
Corpus ID: 15729777
This paper presents an approach to the automatic mapping of arbitrary combinational circuits to the arithmetic carry-chain…
Expand
2009
2009
Feature extraction using coordinate logic filters and Artificial Neural Networks
J. Quintanilla-Domínguez
,
M. Sanchez-Garcia
,
M. Gozalez-Romo
,
A. Vega-Corona
,
D. Andina
7th IEEE International Conference on Industrial…
2009
Corpus ID: 18819936
This paper presents a novel feature extraction method using the combination of the Coordinate Logic Filters (CLF) and Artificial…
Expand
2008
2008
Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs
Michael T. Frederick
,
Arun Kumar Somani
Symposium on Field Programmable Gate Arrays
2008
Corpus ID: 5325419
Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and…
Expand
2007
2007
A 45 PS Time-Interval Counter Board with a PCI Interface
R. Szplet
,
J. Kalisz
,
Z. Jachna
,
K. Rozyc
2007
Corpus ID: 60088882
Abstract : This paper describes the design and test results of a precise time-interval and frequency counter board with PCI…
Expand
1994
1994
Techniques for fast CMOS-based conditional sum adders
Hannes Lindkvist
,
P. Andersson
Proceedings IEEE International Conference on…
1994
Corpus ID: 8904766
Conditional sum adders, CSAs, and carry-lookahead adders, CLAs, both have logarithmic gate depth. However, CLAs require a final…
Expand
1965
1965
Method in randomness
M. Greenberger
CACM
1965
Corpus ID: 18553503
where 9 signifies any significant hit and the leftmost g in the left cell could be 1. Note that the inequalities (12) show axb…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE
or Only Accept Required