Bus mastering

Known as: Bus arbitration, Bus arbiter, First party DMA 
In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate transactions. It… (More)
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Topic mentions per year

Topic mentions per year

1981-2015
02419812015

Papers overview

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2016
2016
System on Chip (SoC) integrates heterogeneous elements like memory, DSPs, timing sources, ADCs, DACs etc. on a silicon chip. One… (More)
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2012
2012
  • Ray Bittner
  • 22nd International Conference on Field…
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PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in… (More)
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2011
2011
The standard paradigm in Real Time Ethernet systems is the master/slave configuration and although intrinsically allowed by many… (More)
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2009
2009
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak… (More)
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2008
2008
A very common problem which affects the performance of bus-based computing systems arises from the fact that the bus is a common… (More)
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2005
2005
Contention detection and resolution procedure is presented. This procedure is tailored for use over the direct current (DC) power… (More)
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2003
2003
This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters… (More)
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2000
2000
An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access… (More)
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1993
1993
 
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