FAQ

Bus mastering

Known as: Bus arbitration, Bus arbiter, First party DMA 
In computing, bus mastering is a feature supported by many bus architectures that enables a device connected to the bus to initiate transactions. It… (More)
Wikipedia

Topic mentions per year

Topic mentions per year

1981-2015
02419812015

Related topics

Related topics

26 relations
AMD Lance Am7990Channel I/OControl busConventional PCI
(More)

Broader (1)

Motherboard

Related mentions per year

Related mentions per year

1960-2018
1960198020002020
Bus mastering
Operating system
Conventional PCI
Real-time operating system
Device driver
Direct memory access

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Comparative analysis of different lottery bus arbitration techniques for SoC communication
System on Chip (SoC) integrates heterogeneous elements like memory, DSPs, timing sources, ADCs, DACs etc. on a silicon chip. One… (More)
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2012
2012
Speedy bus mastering PCI express
  • Ray Bittner
  • 22nd International Conference on Field…
  • 2012
PCI Express is a ubiquitous bus interface providing the highest bandwidth connection in the PC platform. Sadly, support for it in… (More)
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2011
2011
Embedding Real Time Ethernet: Examining feasibility of separating bus master and application master in industrial POWERLINK implementations
The standard paradigm in Real Time Ethernet systems is the master/slave configuration and although intrinsically allowed by many… (More)
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2009
2009
Bus mastering PCI express in an FPGA
This paper describes a bus mastering implementation of the PCI Express protocol using a Xilinx FPGA. While the theoretical peak… (More)
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2008
2008
A dedicated DMA logic addressing a time multiplexed memory to reduce the effects of the system bus bottleneck
A very common problem which affects the performance of bus-based computing systems arises from the fact that the bus is a common… (More)
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2005
2005
New Software for NanoHarp 250 Multichannel Scaler/Photon Counter
 
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2005
2005
A new multiple access scheme for DC power line communications
Contention detection and resolution procedure is presented. This procedure is tailored for use over the direct current (DC) power… (More)
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2003
2003
A methodology for the design of AHB bus master wrappers
This paper proposes a methodology and a basic structure for the design of wrappers used to adapt cores for use as bus masters… (More)
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2000
2000
Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core
An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access… (More)
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1993
1993
Analysis and simulation of six bus arbitration protocols
 
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