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Bit cell

A bit cell is the length of tape, the area of disc surface, or the part of an integrated circuit in which a single bit is recorded. The smaller the… 
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Areal density (computer storage)CodeComputer data storageDisk storage

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs
  • A. BhojN. Jha
  • IEEE Transactions on Very Large Scale Integration…
  • 2014
  • Corpus ID: 29939679
Multigate FET technology is the most viable successor to planar CMOS technology at the 22-nm node and beyond. Prior research on… 
2011
2011
Embedded memory fail analysis for production yield enhancement
The traditional approach for memory fail bitmap analysis is to identify the topological signatures and perform a Failure Analysis… 
2010
2010
A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and… 
Highly Cited
2006
Highly Cited
2006
Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65 nm CMOS Technology
Accelerated alpha-soft error rate (SER) measurements are carried out on regular and radiation-hardened SRAMs in a 65 nm CMOS… 
Highly Cited
2005
Highly Cited
2005
Analyzing static noise margin for sub-threshold SRAM in 65nm CMOS
This paper evaluates the static noise margin (SNM) of 6T SRAM bitcells operating in sub-threshold. We analyze the dependence of… 
2005
2005
The design, analysis, and development of highly manufacturable 6-T SRAM bitcells for SoC applications
We present here an extensive static random access memory (SRAM) bitcell development methodology that has led to the qualification… 
2004
2004
FIB Failure analysis of memory arrays
2004
2004
Drain disturb during CHISEL programming of NOR flash EEPROMs-physical mechanisms and impact of technological parameters
The origin of drain disturb in NOR Flash EEPROM cells under channel initiated secondary electron (CHISEL) programming operation… 
1999
1999
Recording heads with track widths suitable for 100 Gbit/in/sup 2/ density
Focused ion beam etching has been used to trim both longitudinal and perpendicular recording heads with track widths as narrow as… 
1997
1997
Considerations In The Design Of Probe Heads For 100 Gbit/in/sup 2/ Recording Density
Thin film perpendicular playback yoke-GMR heads capable of reading at a density of 100 Gbit/in/sup 2/ have been designed using 3D… 
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