Skip to search formSkip to main contentSkip to account menu

Bit cell

A bit cell is the length of tape, the area of disc surface, or the part of an integrated circuit in which a single bit is recorded. The smaller the… 
Wikipedia (opens in a new tab)

Related topics

Related topics

9 relations
Areal density (computer storage)CodeComputer data storageDisk storage

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
READ STABILITY ANALYSIS OF 6 T SRAM BIT CELL
Static Random Access Memory (SRAM) cell stability is the important concern in nanometre technologies due to the intra-die… 
2014
2014
subthreshold SRAM bit cell topologies for ultra low power applications
  • Mahipal DargupallyT. Reddy
  • 2014
  • Corpus ID: 63674796
Ultra Low Power is one of the major concern in VLSI Industry recent years. One of the technique which used to improve the concept… 
2013
2013
Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control
SRAM bitcell optimizations have been demonstrated in 28nm High-k Metal Gate UTBB (Ultra-Thin Body and BOX) FD-SOI technology. The… 
2011
2011
Adiabatic 5T SRAM
In this paper an effort is made to design an energy efficient 5T SRAM in 65nm technology. The energy recovery driver saves energy… 
2011
2011
D EEP S UB -M ICRON SRAM D ESIGN FOR DRV A NALYSIS AND L OW L EAKAGE
This paper deals with the design opportunities of Static Random Access Memory (SRAM) for lower power consumption and propagation… 
2010
2010
1.5 GHz robust SRAM array employing dynamic power management scheme
A low power SRAM macro is customized in 90nm TSMC model technology. The design minimizes the area of the bitcells to achieve a… 
2010
2010
Linear and non-linear contributions to the visual sensitivity of neurons in primate lateral geniculate nucleus
Several parallel pathways convey retinal signals to the visual cortex of primates. The signals of the parvocellular (P) and… 
2009
2009
16Mb Split Gate Flash Memory with Improved Process Window
  • J. YaterM. Suhail Gowrishankar L. Chindalore
  • IEEE International Memory Workshop
  • 2009
  • Corpus ID: 8286654
This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array… 
2009
2009
High-density 3-D metal-fuse PROM featuring 1.37µm2 1T1R bit cell in 32nm high-k metal-gate CMOS technology
A 4Kbit high-density PROM array design featuring a high-volume manufacturable metal-fuse technology in 32nm high-k metal-gate… 
2007
2007
Modeling SRAM Failure Rates to Enable Fast , Dense , Low-Power Caches 1 Architecture Technology Group
The embedded memory hierarchy of microprocessors and systems-on-a-chip plays a critical role in the overall system performance…