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Abstract A new idea for a binary clock is presented. It displays the time using a triangular array of 15 lamps each representing… Expand In today's circuit designs, with increasing density of devices and fast augmentation of clock frequencies, low-power design is a… Expand Period jitter plays a critical role in global clock distribution design, because it directly impacts the time available for logic… Expand As device dimensions shrink to deep sub-micron ranges, the hot-carrier effect is a main concern for the long-term reliability. It… Expand Period jitter plays a critical role in global clock distribution, because it directly impacts the time available for logic… Expand This paper explores an activity-sensitive clock gating technique for low-power design of VLSI clock networks. The concept of… Expand This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We… Expand An exponentially small upper bound on the probability that a given binary string of length $n$ can be embedded into a uniformly… Expand A novel technique for designing binary clock trees with reduced delay and near-zero skew is described. Starting with the minimum… Expand Two designs of a fault-tolerant clocking system are described: a time-discrete design based on autonomous oscillators and a time… Expand