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2016

2016

Abstract A new idea for a binary clock is presented. It displays the time using a triangular array of 15 lamps each representing… Expand

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2015

2015

In today's circuit designs, with increasing density of devices and fast augmentation of clock frequencies, low-power design is a… Expand

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2012

2012

Period jitter plays a critical role in global clock distribution design, because it directly impacts the time available for logic… Expand

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2012

2012

This article describes an inexpensive way of clock generation for FPGA-based circuit cores, which reduces the number of external… Expand

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2009

2009

As device dimensions shrink to deep sub-micron ranges, the hot-carrier effect is a main concern for the long-term reliability. It… Expand

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2008

2008

Period jitter plays a critical role in global clock distribution, because it directly impacts the time available for logic… Expand

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2007

2007

This paper explores an activity-sensitive clock gating technique for low-power design of VLSI clock networks. The concept of… Expand

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2002

2002

This paper presents an activity-sensitive clock tree construction technique for low power design of VLSI clock networks. We… Expand

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1996

1996

An exponentially small upper bound on the probability that a given binary string of length $n$ can be embedded into a uniformly… Expand

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1993

1993

A novel technique for designing binary clock trees with reduced delay and near-zero skew is described. Starting with the minimum… Expand

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