Skip to search form
Skip to main content
Skip to account menu
Semantic Scholar
Semantic Scholar's Logo
Search 225,818,112 papers from all fields of science
Search
Sign In
Create Free Account
Binary clock
Known as:
Binary Watch
, Binary clocks
A binary clock is a clock that displays the time of day in a binary format. Originally, such clocks showed each decimal digit of sexagesimal time as…
Expand
Wikipedia
(opens in a new tab)
Create Alert
Alert
Related topics
Related topics
3 relations
Analog signal
Binary-coded decimal
Digital data
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Ternary Clock Signal Generation Using Binary Clock Signals
V. T. Gaikwad
International Conference on Inventive Research in…
2018
Corpus ID: 57378721
Since inception, almost discrete systems are working on binary logic. These systems are best till date, however to conform the…
Expand
2016
2016
The Triangular Binary Clock
J. Pretz
2016
Corpus ID: 124171004
Abstract A new idea for a binary clock is presented. It displays the time using a triangular array of 15 lamps each representing…
Expand
2015
2015
SAT based low power scheduling and module binding with clock gating
K. Chandrakar
,
Shashank Mishra
,
Suchismita Roy
International Conference on Computer…
2015
Corpus ID: 15217646
In today's circuit designs, with increasing density of devices and fast augmentation of clock frequencies, low-power design is a…
Expand
2012
2012
Compact Expressions for Supply Noise Induced Period Jitter of Global Binary Clock Trees
Jinwook Jang
,
O. Franza
,
W. Burleson
IEEE Transactions on Very Large Scale Integration…
2012
Corpus ID: 7925358
Period jitter plays a critical role in global clock distribution design, because it directly impacts the time available for logic…
Expand
2012
2012
Discrete Fractional Clock Generation for Systems-on-FPGA
Thomas B. Preußer
,
Steffen Köhler
2012
Corpus ID: 55287827
This article describes an inexpensive way of clock generation for FPGA-based circuit cores, which reduces the number of external…
Expand
2009
2009
Synthesis of Anti-Aging Gated Clock Designs
Shih-Hsu Huang
,
Chun-Hua Cheng
,
Song-Bin Pan
Journal of information science and engineering
2009
Corpus ID: 18943180
As device dimensions shrink to deep sub-micron ranges, the hot-carrier effect is a main concern for the long-term reliability. It…
Expand
2008
2008
Compact expressions for period jitter of global binary clock trees
Jinwook Jang
,
O. Franza
,
W. Burleson
IEEE-EPEP Electrical Performance of Electronic…
2008
Corpus ID: 24237116
Period jitter plays a critical role in global clock distribution, because it directly impacts the time available for logic…
Expand
2007
2007
Activity-sensitive clock design for low power consumption
C. Kang
,
Chunhong Chen
Canadian journal of electrical and computer…
2007
Corpus ID: 565426
This paper explores an activity-sensitive clock gating technique for low-power design of VLSI clock networks. The concept of…
Expand
1996
1996
Constrained Embedding Probability for Two Binary Strings
J. Golic
SIAM Journal on Discrete Mathematics
1996
Corpus ID: 21090902
An exponentially small upper bound on the probability that a given binary string of length $n$ can be embedded into a uniformly…
Expand
1993
1993
Skew reduction in clock trees using wire width optimization
N. Menezes
,
A. Balivada
,
S. Pullela
,
L. Pillage
Proceedings of IEEE Custom Integrated Circuits…
1993
Corpus ID: 62463361
A novel technique for designing binary clock trees with reduced delay and near-zero skew is described. Starting with the minimum…
Expand
By clicking accept or continuing to use the site, you agree to the terms outlined in our
Privacy Policy
(opens in a new tab)
,
Terms of Service
(opens in a new tab)
, and
Dataset License
(opens in a new tab)
ACCEPT & CONTINUE