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Arithmetic underflow
Known as:
Integer underflow
, Underflow
The term arithmetic underflow (or "floating point underflow", or just "underflow") is a condition in a computer program where the result of a…
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Related topics
Related topics
17 relations
Binary-coded decimal
Denormal number
Division by zero
Hypot
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
A Markov decision based rate adaption approach for dynamic HTTP streaming
Chao Zhou
,
Chia-Wen Lin
Visual Communications and Image Processing
2015
Corpus ID: 17512304
In this paper, we propose a novel Markov decision-based rate adaption scheme for DASH aiming to maximize the quality of user…
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2015
2015
Ckylark: A More Robust PCFG-LA Parser
Yusuke Oda
,
Graham Neubig
,
S. Sakti
,
Tomoki Toda
,
Satoshi Nakamura
North American Chapter of the Association for…
2015
Corpus ID: 9001123
This paper describes Ckylark, a PCFG-LA style phrase structure parser that is more robust than other parsers in the genre. PCFG…
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2013
2013
Design and Simulation of Floating Point Multiplier Based on VHDL
Remadevi R
2013
Corpus ID: 6426637
Multiplying floating point numbers is a critical requirement for DSP applications involving large dynamic range. This paper…
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Highly Cited
2005
Highly Cited
2005
Performance evaluation of MPEG-4 video streaming over UMTS networks using an integrated tool environment
A. Lo
,
G. Heijenk
,
I. Niemegeers
2005
Corpus ID: 15580153
Universal Mobile Telecommunications System (UMTS) is a third-generation mobile communications system that supports wireless…
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2004
2004
A DNA Arithmetic Logic Unit
F. D. Santis
,
Gennaro Iaccarino
2004
Corpus ID: 196055665
: - We propose in vitro algorithms using Dna strands to perform arithmetic and logical operations. The salient feature of our…
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1989
1989
Multistep Gradual Rounding
Corinna G. Lee
IEEE Trans. Computers
1989
Corpus ID: 5429706
A value V is to be rounded to an arbitrary precision resulting in the value V". Conventional rounding technique uses one step to…
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1989
1989
Digital phase-locked loop with jitter bounded
S. M. Walters
,
T. Troudet
1989
Corpus ID: 110862442
A design of an all-digital phase-locked loop (DPLL) with direct frequency synthesis is proposed for generating signals that…
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1981
1981
An Overflow/Underflow-Free Floating-Point Representation of Numbers.
Matsui Shouichi
,
Iri Masao
1981
Corpus ID: 60764754
1971
1971
Synchronization of communicating processes
A. N. Habermann
Symposium on Operating Systems Principles
1971
Corpus ID: 52859191
This paper appears in the March, 1972, issue of the Communications of the ACM. Its abstract is reproduced below. Formalization…
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1966
1966
Recharge studies on the High Plains in northern Lea County, New Mexico
J. Havens
1966
Corpus ID: 127828239
The area described in this report is that part of the southern High Plains principally within northern Lea County, N. Mex.; it…
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