# Analog multiplier

## Papers overview

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2016

2016

- International Conference on Signal andâ€¦
- 2016

This paper presents two different implementations of four Quadrant CMOS Analog Multiplier Circuits. The Multipliers are designedâ€¦Â (More)

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2011

2011

- 2011

A novel four-quadrant analog multiplier using floating gate MOS (FGMOS) transistors operating in the saturation region isâ€¦Â (More)

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2008

2008

- 2008

Versatile dual-mode class-AB CMOS four-quadrant analog multiplier circuit is presented. The dual translinear loops and currentâ€¦Â (More)

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2005

2005

- IEEE International Symposium on Circuits andâ€¦
- 2005

In this paper, an all NMOS voltage-mode four-quadrant analog multiplier, based on a basic NMOS differential amplifier that canâ€¦Â (More)

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2004

2004

- IEEE International Symposium on Communicationsâ€¦
- 2004

In this paper, a CMOS analog multiplier circuit is proposed. It consists of eight voltage subtractors, four voltage sources and aâ€¦Â (More)

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1987

1987

- 1987

A four-quadrant CMOS analog multiplier is presented. The device is nominafly biased with +5-V supplies, has identicaf full-scafeâ€¦Â (More)

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Highly Cited

1986

Highly Cited

1986

- 1986

,4Mrad â€”A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the squareâ€¦Â (More)

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1985

1985

- IEEE Journal of Solid-State Circuits
- 1985

A novel technique is presented for performing the analog multiplication in CMOS technology. The circuit handles a wide range ofâ€¦Â (More)

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1982

1982

- IEEE Journal of Solid-State Circuits
- 1982

A four-quadrant NMOS analog multiplier, which achieves linearity better than 0.3 percent at 75 percent of full-scale swing, aâ€¦Â (More)

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1961

1961

- IRE Trans. Electronic Computers
- 1961

In the time-division multiplier the product xl x2 is an unpleasant phenomenon is often encountered in formed by pulse-durationâ€¦Â (More)

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