High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme

@article{Wu2020HighSpeedPC,
  title={High-Speed Power-Efficient Coarse-Grained Convolver Architecture using Depth-First Compression Scheme},
  author={Yi-Lin Wu and Yi Lu and Juinn-Dar Huang},
  journal={2020 IEEE International Symposium on Circuits and Systems (ISCAS)},
  year={2020},
  pages={1-5},
  url={https://api.semanticscholar.org/CorpusID:224908147}
}
This paper proposes a high-speed power-efficient convolver architecture for CNN acceleration that features a globally delay-optimized partial product reduction tree and a depth-first compression scheme for both area and power minimization.
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