Skip to search formSkip to main content
You are currently offline. Some features of the site may not work correctly.

Wafer backgrinding

Known as: Backlap, Wafer thinning 
Wafer backgrinding is a semiconductor device fabrication step during which wafer thickness is reduced to allow for stacking and high density… Expand
Wikipedia

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Capacitive micromachined ultrasonic transducers (CMUTs) exhibit wide-bandwidth and can be made into tiny 2-D arrays that are… Expand
  • figure 1
  • table I
  • figure 2
  • figure 3
  • figure 5
Is this relevant?
Highly Cited
2013
Highly Cited
2013
This paper presents ultra-thin silicon chips (flex-chips) on flexible foils, realized through post-processing steps such as wafer… Expand
  • figure 2
  • figure 1
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
Highly Cited
2010
Highly Cited
2010
Pre-bond test is preferred for a three-dimensional integrated circuit (3D IC), since it reduces stacking yield loss and thus… Expand
  • figure 1
  • figure 2
  • figure 4
  • figure 3
  • figure 5
Is this relevant?
2008
2008
This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter… Expand
  • figure 2
  • figure 1
  • figure 3
  • figure 6
  • figure 4
Is this relevant?
2008
2008
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through… Expand
  • figure 1
  • figure 3
  • figure 2
  • figure 7
  • figure 5
Is this relevant?
Highly Cited
2007
Highly Cited
2007
Three dimensional stacked circuits having multiple active semiconductor levels rely on the development of strata bonding, micro… Expand
  • figure 1
  • figure 2
  • figure 3
Is this relevant?
Highly Cited
2006
Highly Cited
2006
A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip… Expand
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 6
Is this relevant?
Highly Cited
2006
Highly Cited
2006
Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other… Expand
  • figure 2
  • figure 1
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
2005
2005
Abstract Sediments of the mid‐Pliocene (c. 3.4–3.0 Ma) Tangahoe Formation exposed in cliffs along the South Taranaki coastline of… Expand
Is this relevant?
2004
2004
A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a… Expand
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 8
Is this relevant?