Wafer backgrinding

Known as: Backlap, Wafer thinning 
Wafer backgrinding is a semiconductor device fabrication step during which wafer thickness is reduced to allow for stacking and high density… (More)
Wikipedia

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Silicon interposers with through silicon vias (TSVs) have become important key components of 3D architectures. They are used as… (More)
  • figure 1
  • figure 3
  • figure 2
  • figure 4
  • figure 5
Is this relevant?
2011
2011
Three-dimensional (3D) integration of electronics and/or MEMS-based transducers is an emerging technology that vertically… (More)
  • figure 1
  • figure 3
  • figure 2
  • figure 4
  • figure 5
Is this relevant?
2009
2009
With the ever-growing number of MEMS resonator applications, an research effort is required. One important step to consider in… (More)
  • figure 2
  • figure 1
  • figure 3
  • figure 5
  • figure 6
Is this relevant?
2009
2009
High frequency characterization and modeling of Through Silicon Vias (TSVs) for new 3D chip staking are presented in this paper… (More)
  • figure 1
  • figure 2
  • table I
  • figure 4
  • figure 3
Is this relevant?
2008
2008
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through… (More)
  • figure 1
  • figure 3
  • figure 2
  • figure 7
  • figure 5
Is this relevant?
2008
2008
Telecommunication equipment that supports high-level information networks is being made portable, small and lightweight. Thus… (More)
  • table 1
  • figure 1
  • figure 3
  • figure 2
  • figure 4
Is this relevant?
2007
2007
Three dimensional stacked circuits having multiple active semiconductor levels rely on the development of strata bonding, micro… (More)
  • figure 1
  • figure 2
  • figure 3
Is this relevant?
Highly Cited
2006
Highly Cited
2006
Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other… (More)
  • figure 2
  • figure 1
  • figure 3
  • figure 4
  • figure 5
Is this relevant?
Highly Cited
2006
Highly Cited
2006
A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 6
Is this relevant?
2004
2004
A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a… (More)
  • figure 1
  • figure 2
  • figure 3
  • figure 4
  • figure 8
Is this relevant?