Skip to search formSkip to main contentSkip to account menu

Wafer backgrinding

Known as: Backlap, Wafer thinning 
Wafer backgrinding is a semiconductor device fabrication step during which wafer thickness is reduced to allow for stacking and high density… 
Wikipedia (opens in a new tab)

Related topics

Related topics

7 relations
Back end of lineBack-illuminated sensorEtching (microfabrication)Microelectromechanical systems

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Fabrication of a Curved Row–Column Addressed Capacitive Micromachined Ultrasonic Transducer Array
Capacitive micromachined ultrasonic transducers (CMUTs) exhibit wide-bandwidth and can be made into tiny 2-D arrays that are… 
Highly Cited
2010
Highly Cited
2010
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding
Pre-bond test is preferred for a three-dimensional integrated circuit (3D IC), since it reduces stacking yield loss and thus… 
Review
2009
Review
2009
Testing 3D chips containing through-silicon vias
Today's miniaturization and performance requirements result in the usage of high-density integration and packaging technologies… 
Review
2008
Review
2008
Wafer-level 3D integration technology
An overview of wafer-level three-dimensional (3D)) integration technology is provided. The basic reasoning for pursuing 3D… 
2008
2008
Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through… 
Highly Cited
2008
Highly Cited
2008
Enabling technologies for 3D chip stacking
This paper presents several key technologies developed for high density 3D integration by circuit stacking, i.e. with an inter… 
Highly Cited
2006
Highly Cited
2006
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
A three-dimensional (3-D) integration technology has been developed for the fabrication of a new 3-D shared-memory test chip… 
Highly Cited
2006
Highly Cited
2006
3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk-Si die containing 10 μm pitch through-Si vias
Using standard single damascene type techniques on bulk-Si, combined on one hand with extreme wafer thinning and on the other… 
2005
2005
An integrated sequence stratigraphic, palaeoenvironmental, and chronostratigraphic analysis of the Tangahoe Formation, southern Taranaki coast, with implications for mid‐Pliocene (c. 3.4–3.0 Ma…
Abstract Sediments of the mid‐Pliocene (c. 3.4–3.0 Ma) Tangahoe Formation exposed in cliffs along the South Taranaki coastline of… 
2004
2004
Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development
A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)