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Tensilica Instruction Extension

Known as: Tie 
Tensilica Instruction Extension refers to the proprietary language that is used to customize the Xtensa processor core architecture. By using TIE… 
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Related topics

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6 relations
C++Computer programmingHardware description languageList of programming languages

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Flexible architectures for retinal blood vessel segmentation in high-resolution fundus images
Blood vessel segmentation from high-resolution fundus images is a necessary step in several retinal pathologies detection… 
2018
2018
Accelerating Hash Computations Through Efficient Instruction-Set Customisation
Security has become a part of our everyday life due to the breakthrough technologies of wireless communication, e-commerce and… 
2018
2018
An Efficient Single Core Flexible Processor Architecture for 4096-bit Montgomery Modular Multiplication and Exponentiation
This paper presents timing efficient and low cost hardware customization of a single core general purpose processor architecture… 
2014
2014
An ASIP approach for interpolation performance enhancement in HEVC decoder
In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high… 
2010
2010
Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms
This work investigates several approaches for implementing the OFDM functions of the fixed-WiMax standard on reconfigurable… 
2009
2009
Method to Design Low-Power Embedded Processor for Wireless Endoscope
This paper describes how to design a suitable micro processor for wireless endoscope. Before designer tune datapath for a… 
2008
2008
Studio e implementazione di strumenti per lo sviluppo software nei sistemi basati su FPGA
Computer market becomes every day more performance-hungry. Nowadays microprocessor based systems are not able to relevant good… 
2003
2003
Logic and Physical Synthesis Methodology for High Performance VLIW / SIMD DSP Core
We describe logic and physical synthesis methodology to achieve timing closure on a high-end VLIW/SIMD DSP processor core. The… 
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