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Symbolic trajectory evaluation
Symbolic trajectory evaluation (STE) is a lattice-based model checking technology that uses a form of symbolic simulation. STE is essentially used…
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3 relations
Electronic circuit
Model checking
Symbolic simulation
Papers overview
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2018
2018
Symbolic Trajectory Evaluation
T. Melham
Handbook of Model Checking
2018
Corpus ID: 44076599
Symbolic trajectory evaluation is an industrial-strength formal hardware verification method, based on symbolic simulation, which…
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2017
2017
Symbolic trajectory evaluation for word-level verification: theory and implementation
Supratik Chakraborty
,
Z. Khasidashvili
,
+4 authors
Rakesh Mistry
Formal methods in system design
2017
Corpus ID: 207146699
Symbolic trajectory evaluation (STE) is a model checking technique that has been successfully used to verify many industrial…
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2015
2015
Counting of Visible Foreign Particles in Liquid Injection Based on Trajectory Modelling
Wang Sirui
,
Zhu Qing
,
Xian Ji-an
2015
Corpus ID: 120054033
In order to meet the requirements of counting of visible foreign particles in liquid injection, an automatic visible foreign…
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2007
2007
Towards First-Order Symbolic Trajectory Evaluation
Donglin Li
,
O. Mohamed
,
Sa'ed Abed
IEEE International Symposium on Multiple-Valued…
2007
Corpus ID: 21036970
Symbolic trajectory evaluation (STE) is a symbolic simulation based bounded model checking approach and its computational…
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2006
2006
Towards first-order symbolic trajectory evaluation using MDGs
Donglin Li
2006
Corpus ID: 59678426
SoC design becomes more complex with the increasing amount of different kinds of IPs on the chip. How to ensure correctness of…
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2006
2006
Semantics, Decision Procedures, and Abstraction Refinement for Symbolic Trajectory Evaluation
Jan-Willem Roorda
2006
Corpus ID: 11392383
The rapid growth in hardware complexity has led to a need for formal verification of hardware designs to prevent bugs from…
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2002
2002
Combining ATPG and symbolic simulation for efficient validation of embedded array systems
G. Parthasarathy
,
Madhu K. Iyer
,
Tao Feng
,
Li-C. Wang
,
K. Cheng
,
M. Abadir
Proceedings. International Test Conference
2002
Corpus ID: 15673246
In the past, symbolic trajectory evaluation (STE) has been shown to be effective for verifying individual array blocks. However…
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2000
2000
Validation of PowerPC/sup TM/ custom memories using symbolic simulation
N. Krishnamurthy
,
Andrew K. Martin
,
M. Abadir
,
J. Abraham
Proceedings of the ... IEEE VLSI Test Symposium
2000
Corpus ID: 206856246
This paper describes the use of Symbolic Trajectory Evaluation (STE), a modified form of symbolic simulation, to verify the…
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1999
1999
A methodology for formal hardware verification based on symbolic trajectory evaluation
R. Bryant
,
K. Nelson
1999
Corpus ID: 63935477
Formal methods refer to a class of techniques used to verify hardware systems. The use of formal methods does not guarantee…
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1993
1993
A model checker for statecharts (linking case tools with formal methods)
N. Day
1993
Corpus ID: 60739372
Computer-Aided Software Engineering (CASE) tools encourage users to codify the speciication for the design of a system early in…
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