SerDes

Known as: Deserialize, Serializer/deserializer 
A Serializer/Deserializer (SerDes pronounced sir-deez) is a pair of functional blocks commonly used in high speed communications to compensate for… (More)
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Papers overview

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2017
2017
While four-level pulse amplitude modulation (PAM4) standards are emerging to increase bandwidth density, the majority of… (More)
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2016
2016
A novel multi-chips Fan-out Wafer Level Package (FOWLP) with fine pitch Cu pillar bumps was presented to accommodate volumes of I… (More)
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2015
2015
This paper presents 56Gb/s PAM4 and NRZ SerDes transceivers (TRXs), designed and fabricated in advance CMOS technology… (More)
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2014
2014
Serial data (SerDes) link has been widely used in gigabit rate link, storage applications, telecom, data communications, etc. The… (More)
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2012
2012
When converting a serial program to a parallel program that can run on a Graphics Processing Unit (GPU) the developer must choose… (More)
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2011
2011
In networking systems today data rates are increasing beyond 15Gb/s and yet the installed backplanes are made of low cost… (More)
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2009
2009
The required features of SerDes chips for 100Gbps Ethernet and OTN optical data transmission are discussed. As a baseline… (More)
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2009
2009
A 2.3 to 5GHz LC PLL is implemented in 65nm standard CMOS for 0.6 to 10Gb/s SerDes applications. The LC VCO is measured to have… (More)
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2007
2007
A built-off self-test (BOST) approach is described in which a self-testing FPGA on a device-under-test (DUT) interface board can… (More)
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2004
2004
Gigahertz serialization and deserialization (SERDES) has become a dominant inter-chip and inter-board data transmission technique… (More)
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