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SerDes

Known as: Deserialize, Serializer/deserializer 
A Serializer/Deserializer (SerDes pronounced sir-deez) is a pair of functional blocks commonly used in high speed communications to compensate for… Expand
Wikipedia

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
While four-level pulse amplitude modulation (PAM4) standards are emerging to increase bandwidth density, the majority of… Expand
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2017
2017
Ultra-high speed data links such as 400GbE continuously push transceivers to achieve better performance and lower power… Expand
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2016
2016
A novel multi-chips Fan-out Wafer Level Package (FOWLP) with fine pitch Cu pillar bumps was presented to accommodate volumes of I… Expand
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Highly Cited
2014
Highly Cited
2014
This paper presents a 28 Gb/s multistandard SerDes macro which is fabricated in TSMC 28 nm CMOS process. The transimpedance… Expand
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Highly Cited
2012
Highly Cited
2012
When converting a serial program to a parallel program that can run on a Graphics Processing Unit (GPU) the developer must choose… Expand
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Highly Cited
2011
Highly Cited
2011
This is the first paper describing the IBM Blue Gene/Q interconnection network and message unit. The Blue Gene/Q system is the… Expand
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2009
2009
Fixed-latency serial links find application in trigger and data acquisition systems of high energy physics (HEP) experiments… Expand
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2009
2009
The continuous growth of traffic volumes steadily raises the throughput requirements on the network infrastructure. Additionally… Expand
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Highly Cited
2006
Highly Cited
2006
Chapter 1. History of High Voltage Charge Pump Chapter 2. Basic MOS Device Physics Chapter 3. Basic Operation of a Charge Pump… Expand
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2006
2006
  • M. He, J. Poulton
  • IEEE Journal of Solid-State Circuits
  • 2006
  • Corpus ID: 35482569
A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR… Expand
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