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SerDes

Known as: Deserialize, Serializer/deserializer 
A Serializer/Deserializer (SerDes pronounced sir-deez) is a pair of functional blocks commonly used in high speed communications to compensate for… 
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Related topics

Related topics

21 relations
8b/10b encodingARINC 818Advanced Telecommunications Computing ArchitectureClock recovery

Broader (1)

Digital electronics

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
High-Throughput Big Data Analytics Through Accelerated Parquet to Arrow Conversion
With the advent of high-bandwidth non-volatile storage devices, the classical assumption that database analytics applications are… 
2009
2009
A persistent cross-platform class objects container for C++ and wxWidgets
This paper introduces a new open-source cross-platform software library written in C++ programming language which is able to… 
Review
2007
Review
2007
Challenges and Solutions for Standards-Based Serial 10 Gb/s Backplane Ethernet
The application of Ethernet as a fabric technology in modular platforms has led to interest in the development of a standard set… 
2006
2006
A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver
A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR… 
2004
2004
A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link
A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter… 
2003
2003
Storage Area Network Architectures Technology White Paper
2003
2003
A 62.5 Gb/s multi-standard SerDes IC
This paper describes a 20-lane 62.5 Gb/s SerDes designed as an interface between the 40G, or quad 10G Optics, and a downstream… 
2003
2003
Periodic jitter injection with direct time synthesis by SPP/sub tm/ ATE for serdes jitter tolerance test in production
Controlled amount ofjitter injection into high speed serial bit stream is required for SerDes jitter tolerance test. While jitter… 
2002
2002
Timing jitter measurement of 10 Gbps bit clock signals using frequency division
This paper presents a new method for measuring timing jitter of the bit clock signal in telecommunication devices operating at 10… 
2000
2000
A Terabit Multi-service Switch with Quality of Service Support
The Yuni switch architecture,which will be available in silicon later this year, enablesa scalableswitchingplatform frommulti… 
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