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International Symposium on Physical Design

Known as: ISPD 
The International Symposium on Physical Design, or ISPD is a yearly conference on the topic of electronic design automation, concentrating on… 
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Asia and South Pacific Design Automation ConferenceDesign Automation ConferenceDesign Automation and Test in EuropeElectronic design automation

Papers overview

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2015
2015
Detailed-routability-driven analytical placement for mixed-size designs with technology and region constraints
A placer without considering modern technology and region constraints could generate solutions with irresolvable detailed-routing… 
2015
2015
3-D object detection based on line sets matching
3-D Object detection plays an important role in automation industry. It is a big challenge to detect 3-D object in images without… 
2013
2013
Incorporating the impacts of workload-dependent runtime variations into timing analysis
In the nanometer era, runtime variations due to workload dependent voltage and temperature variations as well as transistor aging… 
2012
2012
Structure based de novo design of IspD inhibitors as anti-tubercular agents
Tuberculosis is one of the leading contagious diseases, caused by Mycobacterium tuberculosis. Despite improvements in anti… 
2010
2010
Minimizing Thermal Disparities during Placement in 3D ICs
During the Computer Aided Physical Design Cycle and specifically for high-performance VLSI circuits, on-chip power density plays… 
2010
2010
Multilevel Optimization for Large-Scale Hierarchical FPGA Placement
This paper proposes a multilevel placer targeted at hierarchical FPGA (Field Programmable Gate Array) devices. The placer is… 
Review
2010
Review
2010
Proceedings of the 19th international symposium on Physical design
On behalf of the organizing committee for the 2010 ACM International Symposium on Physical Design (ISPD), we are delighted to… 
2006
2006
Large Scale Placement with Explicit Cell Movement Control
Nowadays a circuit placement algorithm often faces a problem size of multi-million objects, with excessive fixed blockages. We… 
2006
2006
WIRE-DELAY REDUCTION ANALYSIS OF A 3-TIER , 8-POINT FAST FOURIER TRANSFORM 3 DIC
3D-ICs promise to reduce wire-delays, but non-idealities threaten to diminish the benefit. This paper presents an analysis of the… 
2002
2002
VHDL-AMS modeling of a new PLL with an inverse sine phase detector (ISPD PLL)
For improving the performance of PLL, a sin/sup -1/(x) function generator has been substituted for a standard phase detector. The… 
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