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Intel Core (microarchitecture)
Known as:
Intel Core microarchitecture
, Intel Core 2 Solo ULV
, Intel Core Architecture
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The Intel Core microarchitecture (previously known as the Next-Generation Micro-Architecture) is a multi-core processor microarchitecture unveiled by…
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Related topics
Related topics
50 relations
BIOS
CPU cache
CPU power dissipation
CPUID
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2015
2015
Evaluating the Combined Impact of Node Architecture and Cloud Workload Characteristics on Network Traffic and Performance/Cost
D. Z. Tootaghaj
,
F. Farhat
,
+4 authors
C. Das
IEEE International Symposium on Workload…
2015
Corpus ID: 7971435
The combined impact of node architecture and workload characteristics on off-chip network traffic with performance/cost analysis…
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2011
2011
Energy efficient tiling on a Many-Core Architecture
E. Garcia
,
Daniel A. Orozco
,
G. Gao
2011
Corpus ID: 5971816
Energy efficiency and power consumption have become an imperative requirement in Computer Architecture. The rising multi-core and…
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2011
2011
CAB: Cache Aware Bi-tier Task-Stealing in Multi-socket Multi-core Architecture
Quan Chen
,
Zhiyi Huang
,
M. Guo
,
Jingyu Zhou
International Conference on Parallel Processing
2011
Corpus ID: 4871890
Modern multi-core computers often adopt a multi-socket multi-core architecture with shared caches in each socket. However…
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2009
2009
Characterizing Application Performance Sensitivity to R esource Contention in Multicore Architectures
Haoqiang Jin
,
R. Hood
,
+5 authors
P. Mehrotra
2009
Corpus ID: 6753818
Contention for shared resources in the memory hierarchy can have a profound effect on the performance of applications running on…
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Review
2009
Review
2009
An Encrypt and Decrypt Algorithm Implementation on FPGAs
Ke Wang
Fifth International Conference on Semantics…
2009
Corpus ID: 23763457
Internet Protocol Security (generally shortened to IPSec) is a framework of open standards that provides data confidentiality…
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Highly Cited
2008
Highly Cited
2008
VAST: Virtualization-Assisted Concurrent Autonomous Self-Test
Hiroaki Inoue
,
Yanjing Li
,
S. Mitra
IEEE International Test Conference
2008
Corpus ID: 28490437
Virtualization-assisted concurrent, autonomous self-test, or VAST, enables a multi-/many-core system to test itself, concurrently…
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2007
2007
Executing Stream Joins on the Cell Processor
B. Gedik
,
Philip S. Yu
,
R. Bordawekar
Very Large Data Bases Conference
2007
Corpus ID: 6838569
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core…
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2007
2007
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
M. Bimberg
,
M. B. S. Tavares
,
E. Matúš
,
G. Fettweis
IEEE International Conference on Application…
2007
Corpus ID: 3260776
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed…
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2001
2001
The Naming System Venture
Hans Reiser
2001
Corpus ID: 14346381
For too long the file system has been semantically impoverished in comparison with database and keyword systems. It is time to…
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1985
1985
A temperature- and process-tolerant 64K EEPROM
C. Bill
,
P. Suciu
,
M. Briner
,
D. Rinerson
IEEE Journal of Solid-State Circuits
1985
Corpus ID: 39631727
A 64K EEPROM is described with emphasis on the circuit techniques used to achieve extended temperature operation. The core…
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