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Instruction pipelining
Known as:
Superpipelined
, Pipelined CPU
, Pipeline stalls
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Instruction pipelining is a technique that implements a form of parallelism called instruction-level parallelism within a single processor. It…
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Related topics
Related topics
46 relations
Atmel AVR
Central processing unit
Classic RISC pipeline
Clock rate
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Design and Performance Analysis on Static and Dynamic Pipelined CPU in Course Experiment of Computer Architecture
Guofeng Qin
,
Yue Hu
,
Linyu Huang
,
Yuchen Guo
International Conference on Crowd Science and…
2018
Corpus ID: 52302304
This paper presents a design method of static pipelined CPU and dynamic pipelined CPU with field programable gate array (FPGA) in…
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2012
2012
Leveraging Sharing in Second Level Translation-Lookaside Buffers for Chip Multiprocessors
Yang Li
,
R. Melhem
,
A. Jones
IEEE computer architecture letters
2012
Corpus ID: 7070533
Traversing page table during virtual to physical address translation causes significant pipeline stalls when misses occur in the…
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2002
2002
Fast and Simple Occlusion Culling Using Hardware-based Depth Queries
B. Salomon
,
K. Hillesland
,
A. Lastra
,
Dinesh Manocha
2002
Corpus ID: 14687491
: We present a conservative occlusion culling algorithm for large environments. As part of a preprocess, we decompose the scene…
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1999
1999
Contrasting branch characteristics and branch predictor performance of C++ and C programs
D. Tang
,
A.M.G. Maynard
,
L. John
IEEE International Performance, Computing, and…
1999
Corpus ID: 1664317
In today's superscalar and superpipelined computers, branch instructions are the main culprits that limit the processor from…
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Highly Cited
1998
Highly Cited
1998
A low-power IDCT macrocell for MPEG2 MP@ML exploiting data distribution properties for minimal activity
T. Xanthopoulos
,
A. Chandrakasan
Symposium on VLSI Circuits. Digest of Technical…
1998
Corpus ID: 14383164
This work describes the implementation of a low power IDCT chip targetted to medium and low bitrate applications. Our strategy…
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1998
1998
PERFORMANCE ESTIMATION FOR HARDWARE / SOFTWARE CODESIGN USING HIERARCHICAL COLORED PETRI NETS
ServiceInitiation
,
ServiceDone
,
FD Wswdmw WriteBack
,
MemAccess
1998
Corpus ID: 15681007
This paper presents an approach for abstract modeling of the functional behavior of hardware architectures using Hierarchical…
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1995
1995
Functional Verification of a Multiple-issue, Pipelined, Superscalar Alpha Processor - the Alpha 21164 CPU Chip
M. Kantrowitz
,
L. M. Noack
Digital technical journal of Digital Equipment…
1995
Corpus ID: 14196585
Digital's Alpha 21164 processor is a complex quad-issue, pipelined, superscalar implementation of the Alpha architecture…
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1994
1994
MOVE32INT Architecture and Programmer's Reference Manual
H. Corporaal
1994
Corpus ID: 59764099
The MOVE project at the Faculty of Electrical Engineering of the TU Delft aims at designing and building high-performance…
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1994
1994
Retargetable code generation for parallel, pipelined processor structures
W. Schenk
Code Generation for Embedded Processors
1994
Corpus ID: 14623085
The demand for decreased turn around time in the design of programmable digital circuits requires CAD tools for synthesis…
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1986
1986
Data flow chip ImPP and its system for image processing
M. Iwashita
,
T. Temma
ICASSP '86. IEEE International Conference on…
1986
Corpus ID: 60921053
A data flow image pipelined processor VLSI chip (ImPP:µPD7281) has been developed. Its hardware architecture and the experimental…
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