z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900

@article{Buttlar2002zCECSIMAE,
  title={z/CECSIM: An efficient and comprehensive microcode simulator for the IBM eServer z900},
  author={Joachim von Buttlar and Harald B{\"o}hm and Reinhard Ernst and Axel Horsch and Andreas Kohler and Herbert Schein and Michael Stetter and Klaus Theurich},
  journal={IBM J. Res. Dev.},
  year={2002},
  volume={46},
  pages={607-616}
}
An IBM eServer zSeries™ system uses various types of microcode (firmware) that implement functions such as the execution of complex instructions in the CPUs, I/O operations performed by the system assist processors (SAPs), the management of logical partitions (LPARs), and control by the support element (SE. [] Key Method It executes the instruction stream as completely as possible on the underlying hardware.

Figures and Tables from this paper

IBM eServer z990 improvements in firmware simulation

With the IBM eServerTM z990 system, code simulation efficiency has been improved and code verification is accomplished more easily, more effectively, and with better coverage using Linux debugging features because of the ease of performing functional tests with Linux.

Advanced firmware verification using a code simulator for the IBM System z9

To verify correct implementation of the z/ArchitectureTM, a new test-case framework is introduced called the Verification Interface for System Architecture, or VISA, which is used in simulations as well as on the actual system.

Accelerating system integration by enhancing hardware, firmware, and co-simulation

This paper focuses primarily on the hardware subsystem verification of the CLK chip [which is the interface between the central electronic complex (CEC) and the service element (SE] and on enhanced co-simulation.

IBM eServer z900 system microcode verification by simulation: The virtual power-on process

This paper describes a process, virtual power-on (VPO), which encompasses both hardware and software verification and compares the results achieved with that process with those achieved using previous processes.

Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification

This paper describes a means for addressing a new set of handling, efficiency, and serviceability demands through the use of one of the largest hyper-acceleration systems created thus far, and describes many new associated features that have been implemented in operating software.

Enhanced I/O subsystem recovery and availability on the IBM System z9

An overview of recovery and how it interacts with other RAS functions--such as error-detection mechanisms in hardware, including automatic identification and recovery of failing elements--up to the point in time prior to the advent of the z9 is presented.

RAS design for the IBM eServer z900

The z900 RAS enhancements are described and how they strengthen the RAS strategy building blocks and provide a basis for autonomic computing.

IBM Parallel Sysplex design for the IBM z196 system

The latest generation of high-fanout and low-latency coupling adapter cards, the associated firmware, and a new protocol are described, which improve connectivity, latency, and throughput in the IBM System z Parallel Sysplex.

Firmware verification and simulation in IBM zEnterprise 196

Four affected areas are discussed: 1) virtualization of the support element, the hardware management console, and the flexible support processor; 2) test cases; 3) simulation of input/output adapter firmware; and 4) static analysis for millicode.

The GNU 64-bit PL8 compiler: Toward an open standard environment for firmware development

The extension of PL8 to support 64-bit addressing, its implementation as a GCC front end, and the validation of the new compiler are reported on and PL8 is evaluated as a language for highly reliable low-level programming and given some performance data.

References

SHOWING 1-10 OF 15 REFERENCES

IBM eServer z900 I/O subsystem

A common I/O platform is discussed which has been used to provide a uniform, high-bandwidth attachment of industry-standard peripheral computer interface (PCI) cards, while maintaining the leadership functionality and RAS of the eServer zSeries™.

Hyper-acceleration and HW/SW co-verification as an essential part of IBM eServer z900 verification

This paper describes a means for addressing a new set of handling, efficiency, and serviceability demands through the use of one of the largest hyper-acceleration systems created thus far, and describes many new associated features that have been implemented in operating software.

Functional verification of the CMOS S/390 Parallel Enterprise Server G4 system

The methods employed by the functional verification team to demonstrate that its logical system complied with the S/390 architecture while staying within the changing cost structure and time-to-market constraints are described.

Custom S/390 G5 and G6 microprocessors

Compared with the G4 microprocessor, the S/390® G5 microprocessor contains many architectural and performance enhancements, and includes a new IEEE binary floating-point architecture and additional reliability-availability-serviceability (RAS) improvements.

AVPGEN-A test generator for architecture verification

This paper describes a system (AVPGEN) for generating tests to check the conformance of processor designs to the specified architecture and uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques.

Self-timed interface for S/390 I/O subsystem interconnection

The self-timed interface (STI) provides high bandwidth, greater communication distances, and simpler timing within the S/390 servers than traditional interfaces.

Coupling I/O channels for the IBM eServer z900: Reengineering required

The IBM eServer z900 introduces new Parallel Sysplex® coupling channels that satisfy evolving requirements in a way that minimizes product and development costs. Their design also provides backward

A high-frequency custom CMOS S/390 microprocessor

  • C. WebbJ. Liptay
  • Computer Science
    Proceedings International Conference on Computer Design VLSI in Computers and Processors
  • 1997
The S/390 G4 CMOS processor is an implementation of the IBM ESA/390 architecture on a single custom CMOS chip. It is a new design which uses a straightforward pipeline both to achieve a fast cycle

High Level Microprogramming in I370

Hardware is used for the implementation of the performance critical S/370 instructions and microcode for the remainder of the S/ 370 functions.

IBM Corporation, z/VM CMS Application Multitasking, Order No. SC24-5961; available through IBM branch offices

  • IBM Corporation, z/VM CMS Application Multitasking, Order No. SC24-5961; available through IBM branch offices