rdwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects

  title={rdwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects},
  author={K. Goossens and Martijn Bennebroek and Jae Young Hur and M. A. Wahlah},
  journal={Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008)},
We propose that networks on chip (NOC) are hardwired in field-programmable gate arrays (FPGA). Although some area of the FPGA then has a fixed function, this loss of flexibility is outweighed by the following benefits. First, implementation cost is much reduced. Second, a hardwired NOC solves physical problems such as timing closure and high cost of global wiring. Third, dynamic partial reconfiguration can be better exploited. Compared to current soft or firm interconnects, a hardwired NOC… CONTINUE READING
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