Lecture #1: Meeting the Signal Integrity Challenges of High-Speed Designs The intense drive for signal integrity has been at the forefront of rapid and new development in CAD algorithms focused on high-speed circuits and systems. With increasing demands for high signal speeds coupled with decreasing feature sizes, interconnect effects such as signal delay, distortion and crosstalk become the dominant factors limiting the performance of high-speed systems. On the other hand, interconnect structures can be diverse and present at any of the hierarchical packaging levels including integrated circuits, printed circuit boards, multi-chip modules and backplanes. If not considered during the design stage, interconnect effects can cause failed designs. Since extra iterations in the design cycle are costly, accurate prediction of these effects is a necessity in high-speed designs. Although conventional CAD tools such as SPICE are used routinely by many engineers for simulation and general circuit analysis, these tools do not handle adequately the new emerging challenges of interconnect effects.