ZerehCache: Armoring cache architectures in high defect density technologies


Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly sensitive to process variation due to their high density and organization. Designers typically over-provision caches with additional resources to overcome the hard-faults. However… (More)
DOI: 10.1145/1669112.1669127


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